Texas-instruments TMS320C64x DSP Manuel d'utilisateur
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- Page / 306
- Table des matières
- MARQUE LIVRES
- TMS320C64x DSP 1
- Reference Guide 1
- Read This First 3
- Trademarks 4
- Contents 10
- Overview 18
- 1.1 Video Port 19
- Video Port 20
- 1-3OverviewSPRU629 20
- 1.2 Video Port FIFO 22
- 1.3 Video Port Registers 29
- 1.4 Video Port Pin Mapping 30
- 2.1 Reset Operation 35
- 2.1.3 Software Port Reset 36
- 2.1.4 Capture Channel Reset 36
- 2.1.5 Display Channel Reset 37
- 2.2 Interrupt Operation 38
- 2.3 DMA Operation 39
- DMA Operation 41
- Video Port2-8 SPRU629 41
- 2-9Video PortSPRU629 42
- Video Port2-10 SPRU629 43
- 2.3.4 DMA Interface Operation 44
- 2.4 Clocks 45
- 2.5.2 FIFO Size 46
- Table 2–8 54
- Video Capture Port 63
- 3.2 BT.656 Video Capture Mode 65
- 3.2.4 BT.656 Data Sampling 70
- 3.2.5 BT.656 FIFO Packing 71
- BT.656 Video Capture Mode 72
- 3-11Video Capture PortSPRU629 73
- 3.3 Y/C Video Capture Mode 74
- Y/C Video Capture Mode 75
- 3-13Video Capture PortSPRU629 75
- 3.3.4 Y/C FIFO Packing 76
- 3-15Video Capture PortSPRU629 77
- 3-17Video Capture PortSPRU629 79
- 3-21Video Capture PortSPRU629 83
- 3-23Video Capture PortSPRU629 85
- 3.4.4 Field Identification 86
- 3-25Video Capture PortSPRU629 87
- 3.5 Video Input Filtering 88
- 3.5.3 Scaling Operation 89
- 3.5.4 Edge Pixel Replication 91
- 3.6 Ancillary Data Capture 93
- 3.7 Raw Data Capture Mode 94
- 3.7.2 Raw Data FIFO Packing 95
- Raw Data Capture Mode 96
- 3-35Video Capture PortSPRU629 97
- Figure 3–21 98
- 3.8 TSI Capture Mode 99
- 3.8.6 Writing to the FIFO 103
- Figure 3–25. TSI FIFO Packing 103
- 3.8.7 Reading from the FIFO 104
- YDEF YDEFYDEF YDEF 105
- CbDEF CbDEFCrDEF CrDEF 105
- 3.13 Video Capture Registers 111
- Field Descriptions 113
- Video Capture Registers 127
- 3-65Video Capture PortSPRU629 127
- Video Display Port 146
- 4.1.1 Image Timing 147
- 4.1.2 Video Display Counters 150
- 4.1.3 Sync Signal Generation 152
- 4.1.4 External Sync Operation 153
- 4.1.5 Port Sync Operation 153
- 4.2 BT.656 Video Display Mode 154
- 4.2.2 Blanking Codes 157
- 4.2.3 BT.656 Image Display 157
- 4.2.4 BT.656 FIFO Unpacking 158
- BT.656 Video Display Mode 159
- 4-15Video Display PortSPRU629 160
- 4.3 Y/C Video Display Mode 161
- 4.3.2 Y/C Blanking Codes 162
- 4.3.3 Y/C Image Display 162
- 4.3.4 Y/C FIFO Unpacking 162
- Y/C Video Display Mode 163
- 4-19Video Display PortSPRU629 164
- 4.4 Video Output Filtering 166
- 4.4.3 Scaling Operation 167
- 4.4.4 Edge Pixel Replication 168
- Video Output Filtering 169
- 4.5 Ancillary Data Display 170
- 4.6 Raw Data Display Mode 170
- 4.6.2 Raw Data FIFO Unpacking 171
- Raw Data Display Mode 172
- 4-27Video Display PortSPRU629 172
- 4-29Video Display PortSPRU629 174
- 4-33Video Display PortSPRU629 178
- 4.9 Display Timing Examples 180
- Display Timing Examples 181
- 4-36 Video Display Port 181
- 4-37Video Display PortSPRU629 182
- VDTHRLD with a value of 3 184
- 4-40 Video Display Port 185
- 4-41Video Display PortSPRU629 186
- 4-43Video Display PortSPRU629 188
- 4-44 Video Display Port 189
- 4-45Video Display PortSPRU629 190
- 4-47Video Display PortSPRU629 192
- 4-49Video Display PortSPRU629 194
- 4-51Video Display PortSPRU629 196
- 4.12 Video Display Registers 197
- General Purpose I/O Operation 242
- 5.1 GPIO Registers 243
- Chapter 6 268
- 6.1 Overview 269
- 6.2 Interface 270
- 6.3 Operational Details 270
- 6.4 Enabling VIC Port 272
- 6.5 VIC Port Registers 272
- Table 6–4 273
- Appendix A 277
Résumé du contenu
TMS320C64x DSPVideo Port/VCXO Interpolated Control (VIC) PortReference GuideLiterature Number: SPRU629April 2003
Contentsx SPRU6296 VCXO Interpolated Control Port 6-1. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
TSI Capture ModeVideo Capture Port3-38 SPRU629Figure 3–22. Parallel TSI CapturePACSTRTVCLKINCAPENVDIN[9:2]Sync Byte Byte 1 Byte 2 Byte 3 Byte 4Start C
TSI Capture Mode3-39Video Capture PortSPRU629Figure 3–23. Program Clock Reference (PCR) Header Format47 15 14 9 8 0PCRReserved PCR extensionThe video
TSI Capture ModeVideo Capture Port3-40 SPRU629The system time clock counter is initialized by software with the PCR of the firstpacket with a PCR head
TSI Capture Mode3-41Video Capture PortSPRU6293.8.6 Writing to the FIFOThe captured TSI packet data and the associated timestamps are written intothe r
Capture Line Boundary ConditionsVideo Capture Port3-42 SPRU629Figure 3–27. TSI Timestamp Format (Big Endian)63 56 55 48 47 40 39 32PCR(7–0)PCR(15–8) P
Capture Line Boundary Conditions3-43Video Capture PortSPRU629In Figure 3–28 (8-bit Y/C mode), the line length is not a doubleword. When thecondition H
Capturing Video in BT.656 or Y/C ModeVideo Capture Port3-44 SPRU6293.10 Capturing Video in BT.656 or Y/C ModeIn order to capture video in the BT.656 o
Capturing Video in BT.656 or Y/C Mode3-45Video Capture PortSPRU6298) Write to VCxCTL to:- Set capture mode (CMODE = 00x for BT.656 input, 10x for Y/C
Capturing Video in Raw Data ModeVideo Capture Port3-46 SPRU6293.11 Capturing Video in Raw Data ModeIn order to capture video in the raw data mode, the
Capturing Data in TSI Capture Mode3-47Video Capture PortSPRU6293.11.1 Handling FIFO Overrun Condition in Raw Data ModeIn case of a FIFO overrun, the C
FiguresxiFiguresSPRU629Figures1–1 Video Port Block Diagram 1-4. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Capturing Data in TSI Capture ModeVideo Capture Port3-48 SPRU6296) Write to TSISTCMPL, TSISTCMPM, TSISTMSKL, and TSISTMSKM ifneeded to initiate an int
Video Capture Registers3-49Video Capture PortSPRU6293.13 Video Capture RegistersThe registers for controlling the video capture mode of operation are
Video Capture RegistersVideo Capture Port3-50 SPRU629Table 3–13. Video Capture Control Registers (Continued)Acronym SectionRegister NameTSISTCMPL TSI
Video Capture Registers3-51Video Capture PortSPRU629Table 3–14. Video Capture Channel x Status Register (VCxSTAT)Field Descriptions DescriptionBit fi
Video Capture RegistersVideo Capture Port3-52 SPRU629Table 3–14. Video Capture Channel x Status Register (VCxSTAT)Field Descriptions (Continued)BitDes
Video Capture Registers3-53Video Capture PortSPRU6293.13.2 Video Capture Channel A Control Register (VCACTL)Video capture is controlled by the video c
Video Capture RegistersVideo Capture Port3-54 SPRU629Table 3–15. Video Capture Channel A Control Register (VCACTL)Field Descriptions (Continued)Descri
Video Capture Registers3-55Video Capture PortSPRU629Table 3–15. Video Capture Channel A Control Register (VCACTL)Field Descriptions (Continued)Descrip
Video Capture RegistersVideo Capture Port3-56 SPRU629Table 3–15. Video Capture Channel A Control Register (VCACTL)Field Descriptions (Continued)Descri
Video Capture Registers3-57Video Capture PortSPRU629Table 3–15. Video Capture Channel A Control Register (VCACTL)Field Descriptions (Continued)Descrip
Figuresxii SPRU6293–21 20-Bit Raw Data FIFO Packing 3-36. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Video Capture RegistersVideo Capture Port3-58 SPRU6293.13.3 Video Capture Channel x Field 1 Start Register (VCASTRT1, VCBSTRT1)The captured image is a
Video Capture Registers3-59Video Capture PortSPRU629Table 3–16. Video Capture Channel x Field 1 Start Register (VCxSTRT1) Field DescriptionsDescriptio
Video Capture RegistersVideo Capture Port3-60 SPRU6293.13.4 Video Capture Channel x Field 1 Stop Register (VCASTOP1, VCBSTOP1)The video capture channe
Video Capture Registers3-61Video Capture PortSPRU6293.13.5 Video Capture Channel x Field 2 Start Register (VCASTRT2, VCBSTRT2)The captured image is a
Video Capture RegistersVideo Capture Port3-62 SPRU6293.13.6 Video Capture Channel x Field 2 Stop Register (VCASTOP2, VCBSTOP2)The video capture channe
Video Capture Registers3-63Video Capture PortSPRU6293.13.7 Video Capture Channel x Vertical Interrupt Register (VCAVINT, VCBVINT)The video capture cha
Video Capture RegistersVideo Capture Port3-64 SPRU629Table 3–20. Video Capture Channel x Vertical Interrupt Register (VCxVINT)Field DescriptionsDescri
Video Capture Registers3-65Video Capture PortSPRU6293.13.8 Video Capture Channel x Threshold Register (VCATHRLD, VCBTHRLD)The video capture channel x
Video Capture RegistersVideo Capture Port3-66 SPRU629Figure 3–36. Video Capture Channel x Threshold Register (VCATHRLD, VCBTHRLD)31 26 25 16ReservedVC
Video Capture Registers3-67Video Capture PortSPRU6293.13.9 Video Capture Channel x Event Count Register (VCAEVTCT, VCBEVTCT)The video capture channel
FiguresxiiiFiguresSPRU6294–17 10-Bit Y/C FIFO Unpacking 4-19. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Video Capture RegistersVideo Capture Port3-68 SPRU6293.13.10 Video Capture Channel B Control Register (VCBCTL)Video capture is controlled by the video
Video Capture Registers3-69Video Capture PortSPRU629Table 3–23. Video Capture Channel B Control Register (VCBCTL)Field Descriptions (Continued)Descrip
Video Capture RegistersVideo Capture Port3-70 SPRU629Table 3–23. Video Capture Channel B Control Register (VCBCTL)Field Descriptions (Continued)Descri
Video Capture Registers3-71Video Capture PortSPRU629Table 3–23. Video Capture Channel B Control Register (VCBCTL)Field Descriptions (Continued)Descrip
Video Capture RegistersVideo Capture Port3-72 SPRU629Table 3–23. Video Capture Channel B Control Register (VCBCTL)Field Descriptions (Continued)Descri
Video Capture Registers3-73Video Capture PortSPRU629Table 3–24. TSI Capture Control Register (TSICTL) Field DescriptionsDescriptionBit field†symval†Va
Video Capture RegistersVideo Capture Port3-74 SPRU6293.13.12 TSI Clock Initialization LSB Register (TSICLKINITL)The transport stream interface clock i
Video Capture Registers3-75Video Capture PortSPRU6293.13.13 TSI Clock Initialization MSB Register (TSICLKINITM)The transport stream interface clock in
Video Capture RegistersVideo Capture Port3-76 SPRU6293.13.14 TSI System Time Clock LSB Register (TSISTCLKL)The transport stream interface system time
Video Capture Registers3-77Video Capture PortSPRU6293.13.15 TSI System Time Clock MSB Register (TSISTCLKM)The transport stream interface system time c
Figuresxiv SPRU6294–61 Video Display Clipping Register (VDCLIP) 4-85. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4–
Video Capture RegistersVideo Capture Port3-78 SPRU6293.13.16 TSI System Time Clock Compare LSB Register (TSISTCMPL)The transport stream interface syst
Video Capture Registers3-79Video Capture PortSPRU6293.13.17 TSI System Time Clock Compare MSB Register (TSISTCMPM)The transport stream interface syste
Video Capture RegistersVideo Capture Port3-80 SPRU6293.13.18 TSI System Time Clock Compare Mask LSB Register (TSISTMSKL)The transport stream interface
Video Capture Registers3-81Video Capture PortSPRU6293.13.19 TSI System Time Clock Compare Mask MSB Register (TSISTMSKM)The transport stream interface
Video Capture RegistersVideo Capture Port3-82 SPRU6293.13.20 TSI System Time Clock Ticks Interrupt Register (TSITICKS)The transport stream interface s
Video Capture FIFO Registers3-83Video Capture PortSPRU6293.14 Video Capture FIFO RegistersThe capture FIFO mapping registers are listed in Table 3–34.
4-1Video Display PortThe video port peripheral can operate as a video capture port, video displayport, or transport stream interface (TSI) capture por
Video Display Mode SelectionVideo Display Port4-2 SPRU6294.1 Video Display Mode SelectionThe video display module operates in one of three modes as li
Video Display Mode Selection4-3Video Display PortSPRU629Figure 4–1. NTSC Compatible Interlaced DisplayLine 20Line 21Line 22Line 261Line 262Line 263Lin
Video Display Mode SelectionVideo Display Port4-4 SPRU629Figure 4–3. Interlaced Blanking Intervals and Video AreasField 1 Vertical BlankingHorizontal
TablesxvTablesSPRU629Tables1–1 Video Capture Signal Mapping 1-13. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Video Display Mode Selection4-5Video Display PortSPRU629Figure 4–4. Progressive Blanking Intervals and Video AreaField 1 Image WidthField 1FrameField
Video Display Mode SelectionVideo Display Port4-6 SPRU629The image line counter (ILCOUNT) and the image pixel counter (IPCOUNT)track the visible image
Video Display Mode Selection4-7Video Display PortSPRU629Note that the signals can transition at any place along the video line (specifiedby the XSTART
Video Display Mode SelectionVideo Display Port4-8 SPRU6294.1.4 External Sync OperationThe video display module may be synchronized with an external vi
BT.656 Video Display Mode4-9Video Display PortSPRU6294.2 BT.656 Video Display ModeThe BT.656 display mode outputs 8-bit or 10-bit 4:2:2 co-sited luma
BT.656 Video Display ModeVideo Display Port4-10 SPRU629Figure 4–10. 625/50 BT.656 Horizontal Blanking TimingOne Line861 862 863 0 1 2 718 719 720 721
BT.656 Video Display Mode4-11Video Display PortSPRU629Figure 4–11.Digital Vertical F and V TransitionsBlankingOptional blankingLine 4Image: Field 1Bla
BT.656 Video Display ModeVideo Display Port4-12 SPRU6294.2.2 Blanking CodesThe time between the EAV and SAV code on each line represents the horizonta
BT.656 Video Display Mode4-13Video Display PortSPRU6294.2.4 BT.656 FIFO UnpackingDisplay data is always packed into the FIFOs in 64-bit words and must
BT.656 Video Display ModeVideo Display Port4-14 SPRU629For 10-bit BT.656 operation, two samples are unpacked from each word asshown in Figure 4–13.Fig
Tablesxvi SPRU6293–24 TSI Capture Control Register (TSICTL) Field Descriptions 3-73. . . . . . . . . . . . . . . . . . . . . . . . . 3–25 TSI Clock
BT.656 Video Display Mode4-15Video Display PortSPRU629In 10-bit BT.656 dense-pack mode, three samples are unpacked from eachword in the FIFO as seen i
Y/C Video Display ModeVideo Display Port4-16 SPRU6294.3 Y/C Video Display ModeThe Y/C display mode is similar to the BT.656 display mode but outputs 8
Y/C Video Display Mode4-17Video Display PortSPRU6294.3.2 Y/C Blanking CodesThe time between the EAV and SAV code on each line represents the horizon-t
Y/C Video Display ModeVideo Display Port4-18 SPRU629The 8-bit Y/C mode uses three FIFOs for color separation. Four samples areunpacked from each word
Y/C Video Display Mode4-19Video Display PortSPRU629For 10-bit operation, two samples are unpacked from each FIFO word. Thisis shown in Figure 4–17.Fig
Y/C Video Display ModeVideo Display Port4-20 SPRU629In 10-bit Y/C dense-pack mode, three samples are unpacked from each wordin the FIFO as seen in Fig
Video Output Filtering4-21Video Display PortSPRU6294.4 Video Output FilteringThe video output filter performs simple hardware scaling and resampling o
Video Output FilteringVideo Display Port4-22 SPRU6294.4.2 Chrominance Resampling OperationChrominance resampling computes chrominance values at sample
Video Output Filtering4-23Video Display PortSPRU629Figure 4–20. 2x Co-Sited Scaling2× upscaled outputYCbCr 4:2:2 co–sitedsource pixelsLuma (Y)sampleY’
Video Output FilteringVideo Display Port4-24 SPRU629Examples of luma edge and chroma edge replication for 2× interspersed toco-sited output are shown
TablesxviiTablesSPRU6294–26 Video Display Counter Reload Register (VDRELOAD) Field Descriptions 4-83. . . . . . . . . . . . 4–27 Video Display Display
Ancillary Data Display4-25Video Display PortSPRU6294.5 Ancillary Data DisplayThe following sections discuss ancillary data display. No special previsi
Raw Data Display ModeVideo Display Port4-26 SPRU6294.6.1 Raw Mode RGB Output SupportThe raw data display mode has a special pixel count feature that a
Raw Data Display Mode4-27Video Display PortSPRU629For 10-bit operation, two samples are unpacked from each FIFO word. Thisis shown in Figure 4–26.Figu
Raw Data Display ModeVideo Display Port4-28 SPRU629Figure 4–28 shows the 16-bit raw mode. Two samples are unpacked fromeach word of the FIFO.Figure 4–
Raw Data Display Mode4-29Video Display PortSPRU629In 8-bit raw ¾ mode, three samples are unpacked from the FIFO and theremaining byte is ignored. This
Video Display Field and Frame OperationVideo Display Port4-30 SPRU6294.7 Video Display Field and Frame OperationAs a video source, the video port alwa
Video Display Field and Frame Operation4-31Video Display PortSPRU629Table 4–4. Display Operation VDCTL BitCON FRAME DF2 DF1 Operation00 0 0 Reserved0
Video Display Field and Frame OperationVideo Display Port4-32 SPRU629Table 4–4. Display Operation (Continued)VDCTL BitCON OperationDF1DF2FRAME1 0 1 0
Display Line Boundary Conditions4-33Video Display PortSPRU6294.8 Display Line Boundary ConditionsIn order to simplify DMA transfers, FIFO doublewords
Display Line Boundary ConditionsVideo Display Port4-34 SPRU629Figure 4–32. Display Line Boundary ExampleY FIFOCb FIFOY 74Y 76 Y 78Y73Y 75Y 77 Y 79VDOU
1-1OverviewThis chapter provides an overview of the video port peripheral in the digitalsignal processors (DSPs) of the TMS320C6000 DSP family. Inclu
Display Timing Examples4-35Video Display PortSPRU6294.9 Display Timing ExamplesThe following are examples of display output for several modes of opera
Display Timing Examples4-36 Video Display PortSPRU629Figure 4–33. BT.656 Interlaced Display Horizontal Timing Example720 721 722 723 735 736 799 800 8
Display Timing Examples4-37Video Display PortSPRU629The interlaced BT.656 vertical output timing is shown in Figure 4–34. TheBT.656 active field 1 is
Display Timing ExamplesVideo Display Port4-38 SPRU629Figure 4–34. BT.656 Interlaced Display Vertical Timing Example5FLCOUNT525240240ILCOUNTField 1 Bla
Display Timing Examples4-39Video Display PortSPRU6294.9.2 Interlaced Raw Display ExampleThis section shows an example of raw display output for the sa
Display Timing Examples4-40 Video Display PortSPRU629Figure 4–35. Raw Interlaced Display Horizontal Timing Example FLCOUNTVDOUT[19–0] §VCLKOUTVCLKINIP
Display Timing Examples4-41Video Display PortSPRU629The vertical output timing for raw mode is shown in Figure 4–36. This exampleoutputs the same 480-
Display Timing ExamplesVideo Display Port4-42 SPRU629Figure 4–36. Raw Interlaced Display Vertical Timing Example5FLCOUNT525240240ILCOUNTField 1 Blanki
Display Timing Examples4-43Video Display PortSPRU6294.9.3 Y/C Progressive Display ExampleThis section shows an example of progressive display operatio
Display Timing Examples4-44 Video Display PortSPRU629Figure 4–37. Y/C Progressive Display Horizontal Timing Example‡VCLKINFPCOUNTIPCOUNTVCTL1 (HBLNK)†
Video PortOverview1-2 SPRU6291.1 Video PortThe video port peripheral can operate as a video capture port, video displayport, or transport stream inter
Display Timing Examples4-45Video Display PortSPRU629The vertical output timing is shown in Figure 4–38. SMPTE 296M has a singleactive field 1 that is
Display Timing ExamplesVideo Display Port4-46 SPRU629Figure 4–38. Y/C Progressive Display Vertical Timing Example5FLCOUNT750716716ILCOUNTField 1 Blank
Displaying Video in BT.656 or Y/C Mode4-47Video Display PortSPRU6294.10 Displaying Video in BT.656 or Y/C ModeIn order to display video in the BT.656
Displaying Video in BT.656 or Y/C ModeVideo Display Port4-48 SPRU62912) Configure a DMA to move data from the Y buffer in the DSP memory toYDSTA (memo
Displaying Video in Raw Data Mode4-49Video Display PortSPRU62922) If continuous display is enabled, the video port begins displaying again atthe start
Displaying Video in Raw Data ModeVideo Display Port4-50 SPRU62911) Set the horizontal synchronization in VDHSYNC. Specify the frame pixelcounter value
Displaying Video in Raw Data Mode4-51Video Display PortSPRU62922) If continuous display is enabled, the video port begins displaying again atthe start
Video Display RegistersVideo Display Port4-52 SPRU6294.12 Video Display RegistersThe registers for controlling the video display mode of operation are
Video Display Registers4-53Video Display PortSPRU629Table 4–5. Video Display Control Registers (Continued)Acronym SectionRegister NameVDDEFVAL Video D
Video Display RegistersVideo Display Port4-54 SPRU629Table 4–6. Video Display Status Register (VDSTAT) Field DescriptionsBitfield†symval†Value Descrip
IMPORTANT NOTICETexas Instruments Incorporated and its subsidiaries (TI) reserve the right to make corrections,modifications, enhancements, improvemen
Video Port1-3OverviewSPRU629-TSI capture mode: Transport stream interface (TSI) from a front-enddevice such as demodulator or forward error correction
Video Display Registers4-55Video Display PortSPRU6294.12.2 Video Display Control Register (VDCTL)The video display is controlled by the video display
Video Display RegistersVideo Display Port4-56 SPRU629Table 4–7. Video Display Control Register (VDCTL) Field Descriptions (Continued)BitDescriptionVal
Video Display Registers4-57Video Display PortSPRU629Table 4–7. Video Display Control Register (VDCTL) Field Descriptions (Continued)BitDescriptionValu
Video Display RegistersVideo Display Port4-58 SPRU629Table 4–7. Video Display Control Register (VDCTL) Field Descriptions (Continued)BitDescriptionVal
Video Display Registers4-59Video Display PortSPRU629Table 4–7. Video Display Control Register (VDCTL) Field Descriptions (Continued)BitDescriptionValu
Video Display RegistersVideo Display Port4-60 SPRU6294.12.3 Video Display Frame Size Register (VDFRMSZ)The video display frame size register (VDFRMSZ)
Video Display Registers4-61Video Display PortSPRU6294.12.4 Video Display Horizontal Blanking Register (VDHBLNK)The video display horizontal blanking r
Video Display RegistersVideo Display Port4-62 SPRU629Table 4–9. Video Display Horizontal Blanking Register (VDHBLNK) Field DescriptionsDescriptionBit
Video Display Registers4-63Video Display PortSPRU629Figure 4–43. Video Display Field 1 Vertical Blanking Start Register (VDVBLKS1)31 28 27 16ReservedV
Video Display RegistersVideo Display Port4-64 SPRU6294.12.6 Video Display Field 1 Vertical Blanking End Register (VDVBLKE1)The video display field 1 v
Video PortOverview1-4 SPRU629Figure 1–1. Video Port Block DiagramInternal peripheral busMemorymappedregistersRaw videodisplay pipelineChannel BChannel
Video Display Registers4-65Video Display PortSPRU629Table 4–11. Video Display Field 1 Vertical Blanking End Register (VDVBLKE1)Field DescriptionsDescr
Video Display RegistersVideo Display Port4-66 SPRU629Figure 4–45. Video Display Field 2 Vertical Blanking Start Register (VDVBLKS2)31 28 27 16Reserved
Video Display Registers4-67Video Display PortSPRU6294.12.8 Video Display Field 2 Vertical Blanking End Register (VDVBLKE2)The video display field 2 ve
Video Display RegistersVideo Display Port4-68 SPRU629Table 4–13. Video Display Field 2 Vertical Blanking End Register (VDVBLKE2)Field DescriptionsDesc
Video Display Registers4-69Video Display PortSPRU629Figure 4–47. Video Display Field 1 Image Offset Register (VDIMGOFF1)31 30 28 27 16NVReserved IMGVO
Video Display RegistersVideo Display Port4-70 SPRU6294.12.10 Video Display Field 1 Image Size Register (VDIMGSZ1)The video display field 1 image size
Video Display Registers4-71Video Display PortSPRU6294.12.11 Video Display Field 2 Image Offset Register (VDIMGOFF2)The video display field 2 image off
Video Display RegistersVideo Display Port4-72 SPRU629Table 4–16. Video Display Field 2 Image Offset Register (VDIMGOFF2)Field DescriptionsDescriptionB
Video Display Registers4-73Video Display PortSPRU6294.12.12 Video Display Field 2 Image Size Register (VDIMGSZ2)The video display field 2 image size r
Video Display RegistersVideo Display Port4-74 SPRU6294.12.13 Video Display Field 1 Timing Register (VDFLDT1)The video display field 1 timing register
Video Port FIFO1-5OverviewSPRU6291.2 Video Port FIFOThe video port includes a FIFO to store data coming into or out from the videoport. The video port
Video Display Registers4-75Video Display PortSPRU6294.12.14 Video Display Field 2 Timing Register (VDFLDT2)The video display field 2 timing register (
Video Display RegistersVideo Display Port4-76 SPRU6294.12.15 Video Display Threshold Register (VDTHRLD)The video display threshold register (VDTHRLD)
Video Display Registers4-77Video Display PortSPRU629Table 4–20. Video Display Threshold Register (VDTHRLD) Field DescriptionsDescriptionBit field†symv
Video Display RegistersVideo Display Port4-78 SPRU6294.12.16 Video Display Horizontal Synchronization Register (VDHSYNC)The video display horizontal s
Video Display Registers4-79Video Display PortSPRU6294.12.17 Video Display Field 1 Vertical Synchronization Start Register (VDVSYNS1)The video display
Video Display RegistersVideo Display Port4-80 SPRU6294.12.18 Video Display Field 1 Vertical Synchronization End Register (VDVSYNE1)The video display f
Video Display Registers4-81Video Display PortSPRU6294.12.19 Video Display Field 2 Vertical Synchronization Start Register (VDVSYNS2)The video display
Video Display RegistersVideo Display Port4-82 SPRU6294.12.20 Video Display Field 2 Vertical Synchronization End Register (VDVSYNE2)The video display f
Video Display Registers4-83Video Display PortSPRU6294.12.21 Video Display Counter Reload Register (VDRELOAD)When external horizontal or vertical synch
Video Display RegistersVideo Display Port4-84 SPRU6294.12.22 Video Display Display Event Register (VDDISPEVT)The video display display event register
Video Port FIFOOverview1-6 SPRU6291.2.2 Video Capture FIFO ConfigurationsDuring video capture operation, the video port FIFO has one of four configura
Video Display Registers4-85Video Display PortSPRU6294.12.23 Video Display Clipping Register (VDCLIP)The video display clipping register (VDCLIP) is sh
Video Display RegistersVideo Display Port4-86 SPRU6294.12.24 Video Display Default Display Value Register (VDDEFVAL)The video display default display
Video Display Registers4-87Video Display PortSPRU629Figure 4–63. Video Display Default Display Value Register (VDDEFVAL)—Raw Data Mode31 20 19 16Reser
Video Display RegistersVideo Display Port4-88 SPRU6294.12.25 Video Display Vertical Interrupt Register (VDVINT)The video display vertical interrupt re
Video Display Registers4-89Video Display PortSPRU6294.12.26 Video Display Field Bit Register (VDFBIT)The video display field bit register (VDFBIT) con
Video Display RegistersVideo Display Port4-90 SPRU6294.12.27 Video Display Field 1 Vertical Blanking Bit Register (VDVBIT1)The video display field 1 v
Video Display Registers4-91Video Display PortSPRU629Table 4–32. Video Display Field 1 Vertical Blanking Bit Register (VDVBIT1)Field DescriptionsDescri
Video Display RegistersVideo Display Port4-92 SPRU6294.12.28 Video Display Field 2 Vertical Blanking Bit Register (VDVBIT2)The video display field 2 v
Video Display Registers4-93Video Display PortSPRU629Table 4–33. Video Display Field 2 Vertical Blanking Bit Register (VDVBIT2)Field DescriptionsDescri
Video Display Registers Recommended ValuesVideo Display Port4-94 SPRU6294.13 Video Display Registers Recommended ValuesSample recommended values (deci
Video Port FIFO1-7OverviewSPRU629For 8/10-bit raw video, the FIFO is split into channel A and B, as shown inFigure 1–3. Each FIFO is clocked independe
Video Display Registers Recommended Values4-95Video Display PortSPRU629Table 4–34. Video Display Register Recommended Values (Continued)Register 625/5
Video Display FIFO RegistersVideo Display Port4-96 SPRU6294.14 Video Display FIFO RegistersThe display FIFO mapping registers are listed in Table 4–35
5-1General Purpose I/O OperationSignals not used for video display or video capture can be used as general-purpose input/output (GPIO) signals.Topic P
GPIO RegistersGeneral Purpose I/O Operation5-2 SPRU6295.1 GPIO RegistersThe GPIO register set includes required registers such as peripheral identifi-
GPIO Registers5-3General Purpose I/O OperationSPRU6295.1.1 Video Port Peripheral Identification Register (VPPID)The video port peripheral identificati
GPIO RegistersGeneral Purpose I/O Operation5-4 SPRU6295.1.2 Video Port Peripheral Control Register (PCR)The video port peripheral control register (PC
GPIO Registers5-5General Purpose I/O OperationSPRU629Table 5–3. Video Port Peripheral Control Register (PCR) Field DescriptionsBit field†symval†Value
GPIO RegistersGeneral Purpose I/O Operation5-6 SPRU6295.1.3 Video Port Pin Function Register (PFUNC)The video port pin function register (PFUNC) selec
GPIO Registers5-7General Purpose I/O OperationSPRU629Table 5–4. Video Port Pin Function Register (PFUNC) Field Descriptions (Continued)Bit Description
GPIO RegistersGeneral Purpose I/O Operation5-8 SPRU6295.1.4 Video Port Pin Direction Register (PDIR)The video port pin direction register (PDIR) is sh
Video Port FIFOOverview1-8 SPRU629For Y/C video capture, the FIFO is configured as a single channel split into sep-arate Y, Cb, and Cr buffers with se
GPIO Registers5-9General Purpose I/O OperationSPRU629Table 5–5. Video Port Pin Direction Register (PDIR) Field Descriptions (Continued)Bit Description
GPIO RegistersGeneral Purpose I/O Operation5-10 SPRU629Table 5–5. Video Port Pin Direction Register (PDIR) Field Descriptions (Continued)Bit Descripti
GPIO Registers5-11General Purpose I/O OperationSPRU6295.1.5 Video Port Pin Data Input Register (PDIN)The read-only video port pin data input register
GPIO RegistersGeneral Purpose I/O Operation5-12 SPRU629Table 5–6. Video Port Pin Data Input Register (PDIN) Field DescriptionsBit field†symval†Value D
GPIO Registers5-13General Purpose I/O OperationSPRU6295.1.6 Video Port Pin Data Output Register (PDOUT)The video port pin data output register (PDOUT)
GPIO RegistersGeneral Purpose I/O Operation5-14 SPRU629Table 5–7. Video Port Pin Data Out Register (PDOUT) Field DescriptionsBit field†symval†Value De
GPIO Registers5-15General Purpose I/O OperationSPRU6295.1.7 Video Port Pin Data Set Register (PDSET)The video port pin data set register (PDSET) is sh
GPIO RegistersGeneral Purpose I/O Operation5-16 SPRU629Table 5–8. Video Port Pin Data Set Register (PDSET) Field DescriptionsBit field†symval†Value De
GPIO Registers5-17General Purpose I/O OperationSPRU6295.1.8 Video Port Pin Data Clear Register (PDCLR)The video port pin data clear register (PDCLR) i
GPIO RegistersGeneral Purpose I/O Operation5-18 SPRU629Table 5–9. Video Port Pin Data Clear Register (PDCLR) Field DescriptionsBit field†symval†Value
Video Port FIFO1-9OverviewSPRU629For 16/20-bit raw video, the FIFO is configured as a single buffer, as shownin Figure 1–5. The FIFO receives 16/20-bi
GPIO Registers5-19General Purpose I/O OperationSPRU6295.1.9 Video Port Pin Interrupt Enable Register (PIEN)The video port pin interrupt enable registe
GPIO RegistersGeneral Purpose I/O Operation5-20 SPRU629Table 5–10. Video Port Pin Interrupt Enable Register (PIEN) Field DescriptionsBit field†symval†
GPIO Registers5-21General Purpose I/O OperationSPRU6295.1.10 Video Port Pin Interrupt Polarity Register (PIPOL)The video port pin interrupt polarity r
GPIO RegistersGeneral Purpose I/O Operation5-22 SPRU629Table 5–11. Video Port Pin Interrupt Polarity Register (PIPOL) Field DescriptionsBit field†symv
GPIO Registers5-23General Purpose I/O OperationSPRU6295.1.11 Video Port Pin Interrupt Status Register (PISTAT)The video port pin interrupt status regi
GPIO RegistersGeneral Purpose I/O Operation5-24 SPRU629Table 5–12. Video Port Pin Interrupt Status Register (PISTAT) Field DescriptionsBit field†symva
GPIO Registers5-25General Purpose I/O OperationSPRU6295.1.12 Video Port Pin Interrupt Clear Register (PICLR)The video port pin interrupt clear registe
GPIO RegistersGeneral Purpose I/O Operation5-26 SPRU629Table 5–13. Video Port Pin Interrupt Clear Register (PICLR) Field DescriptionsBit field†symval†
6-1VCXO Interpolated Control PortSPRU629VCXO Interpolated Control PortThis chapter provides an overview of the VCXO interpolated control (VIC) port.To
OverviewVCXO Interpolated Control Port6-2 SPRU6296.1 OverviewThe VCXO interpolated control (VIC) port provides single-bit interpolatedVCXO control wit
Video Port FIFOOverview1-10 SPRU629For 8/10-bit raw video, the FIFO is configured as a single buffer as shown inFigure 1–7. The FIFO outputs data on t
Interface6-3VCXO Interpolated Control PortSPRU6296.2 InterfaceThe pin list for VIC port is shown in Table 6–1 (pins are 3.3V I/Os).Table 6–1. VIC Port
Operational DetailsVCXO Interpolated Control Port6-4 SPRU629Any time a packet with a PCR is received, the timestamp for that packet iscompared with th
Enabling VIC Port6-5VCXO Interpolated Control PortSPRU6296.4 Enabling VIC PortPerform the following steps to enable the VIC port.1) Clear the GO bit i
VIC Port RegistersVCXO Interpolated Control Port6-6 SPRU6296.5.1 VIC Control Register (VICCTL)The VIC control register (VICCTL) is shown in Figure 6–3
VIC Port Registers6-7VCXO Interpolated Control PortSPRU629Table 6–4. VIC Control Register (VICCTL) Field Descriptions (Continued)Bit DescriptionValues
VIC Port RegistersVCXO Interpolated Control Port6-8 SPRU6296.5.2 VIC Input Register (VICIN)The DSP writes the input bits for VCXO interpolated control
VIC Port Registers6-9VCXO Interpolated Control PortSPRU6296.5.3 VIC Clock Divider Register (VICDIV)The VIC clock divider register (VICDIV) defines the
A-1Appendix AVideo Port Configuration ExamplesThis appendix describes how to configure the video port in different modeswith the help of examples. All
Example 1: Noncontinuous Frame Capture for 525/60 FormatVideo Port Configuration ExamplesA-2 SPRU629A.1 Example 1: Noncontinuous Frame Capture for 525
Example 1: Noncontinuous Frame Capture for 525/60 FormatA-3Video Port Configuration ExamplesSPRU629/* –––––––––––––––––––––––––––––––––––––––––––– *//
Video Port FIFO1-11OverviewSPRU629Figure 1–8. 8/10 Bit Locked Raw Video Display FIFO ConfigurationBuffer A (2560 bytes)YDSTAVDOUT[9–0]64 8/10Display F
Example 1: Noncontinuous Frame Capture for 525/60 FormatVideo Port Configuration ExamplesA-4 SPRU629/* Error flags
Example 1: Noncontinuous Frame Capture for 525/60 FormatA-5Video Port Configuration ExamplesSPRU629/* Set last pixel to be captured in Field2 (VCA_STO
Example 1: Noncontinuous Frame Capture for 525/60 FormatVideo Port Configuration ExamplesA-6 SPRU629/* –––––––––––––– *//* enable capture *//* –––––––
Example 1: Noncontinuous Frame Capture for 525/60 FormatA-7Video Port Configuration ExamplesSPRU629if(vpis & _VP_VPIS_SFDA_MASK) /* short field de
Example 1: Noncontinuous Frame Capture for 525/60 FormatVideo Port Configuration ExamplesA-8 SPRU629/* Configure Cb EDMA channel to move data from CbS
Example 1: Noncontinuous Frame Capture for 525/60 FormatA-9Video Port Configuration ExamplesSPRU629void configVPCapEDMAChannel(EDMA_Handle *edmaHandle
Example 2: Noncontinuous Frame Display for 525/60 FormatVideo Port Configuration ExamplesA-10 SPRU629A.2 Example 2: Noncontinuous Frame Display for 52
Example 2: Noncontinuous Frame Display for 525/60 FormatA-11Video Port Configuration ExamplesSPRU629/* –––––––––––––––––––––––––––––––––––––––––––––––
Example 2: Noncontinuous Frame Display for 525/60 FormatVideo Port Configuration ExamplesA-12 SPRU629/* –––––––––––––––––––––––––––––––––––––––––– *//
Example 2: Noncontinuous Frame Display for 525/60 FormatA-13Video Port Configuration ExamplesSPRU629/*************************************************
Video Port RegistersOverview1-12 SPRU629For Y/C video display, the FIFO is configured as a single channel split into sep-arate Y, Cb, and Cr buffers w
Example 2: Noncontinuous Frame Display for 525/60 FormatVideo Port Configuration ExamplesA-14 SPRU629/*–––––––––––––––––––––––––––––––––––––––––––––––
Example 2: Noncontinuous Frame Display for 525/60 FormatA-15Video Port Configuration ExamplesSPRU629/* set vertical blanking start for field2 */VP_RS
Example 2: Noncontinuous Frame Display for 525/60 FormatVideo Port Configuration ExamplesA-16 SPRU629/* set vertical sync end for field2 (VCTL2S) */V
Example 2: Noncontinuous Frame Display for 525/60 FormatA-17Video Port Configuration ExamplesSPRU629/* –––––––––––––– *//* enable display *//* –––––––
Example 2: Noncontinuous Frame Display for 525/60 FormatVideo Port Configuration ExamplesA-18 SPRU629/*–––––––––––––––––––––––––––––––––––––––––––––––
Example 2: Noncontinuous Frame Display for 525/60 FormatA-19Video Port Configuration ExamplesSPRU629/* enable three EDMA channels */EDMA_enableChanne
Example 2: Noncontinuous Frame Display for 525/60 FormatVideo Port Configuration ExamplesA-20 SPRU629/* Configure EDMA parameters */EDMA_configArgs(
IndexIndex-1SPRU629IndexAancillary data capture 3-31ancillary data display 4-25architecture 1-3ATC bitin TSISTCMPL 3-78in TSISTCMPM 3-79ATCM bitin TSI
IndexIndex-2 SPRU629CbDEFVAL bits 4-86CBDST 4-96CBSRCx 3-83CCMPA bitin VPIE 2-21in VPIS 2-24CCMPB bitin VPIE 2-21in VPIS 2-24CF1 bitin VCACTL 3-53in
IndexIndex-3SPRU629FF1C bit 3-50F1D bit 4-53F2C bit 3-50F2D bit 4-53FBITCLR bits 4-89FBITSET bits 4-89FIFO overrunBT.656 mode 3-45raw data mode 3-47TS
iiiContentsSPRU629PrefaceRead This FirstAbout This ManualThis document describes the video port and VCXO interpolated control (VIC) portin the digital
Video Port Pin Mapping1-13OverviewSPRU6291.4 Video Port Pin MappingThe video port requires 21 external signal pins for full functionality. Pin usagean
IndexIndex-4 SPRU629LFDE bitin VCACTL 3-53in VCBCTL 3-68Mmode selectionTSI capture 3-2video capture 3-2video display 4-2NNH bitin VDIMGOFF1 4-69in V
IndexIndex-5SPRU629registers (continued)VIC port 6-5VIC clock divider register (VICDIV) 6-9VIC control register (VICCTL) 6-6VIC input register (VICIN)
IndexIndex-6 SPRU629registers (continued)video displayframe size register (VDFRMSZ) 4-60horizontal blanking register(VDHBLNK) 4-61horizontal synchro
IndexIndex-7SPRU629TSI clock initialization LSB register(TSICLKINITL) 3-74TSI clock initialization MSB register(TSICLKINITM) 3-75TSI system time clock
IndexIndex-8 SPRU629VDCLIP 4-85VDCTL 4-55VDDEFVAL 4-86VDDISPEVT 4-84VDEN 4-55VDFBIT 4-89VDFLD bit 4-53VDFLDT1 4-74VDFLDT2 4-75VDFRMSZ 4-60VDHBLNK 4-
IndexIndex-9SPRU629video capture channel B vertical interrupt register(VCBVINT) 3-63video capture FIFO configurations 1-6video capture modeBT.656 3-3r
IndexIndex-10 SPRU629video port FIFO 1-5video port interrupt enable register (VPIE) 2-21video port interrupt status register (VPIS) 2-24video port p
Video Port Pin MappingOverview1-14 SPRU629Table 1–2. Video Display Signal MappingUsageRaw Data Display ModeVideo PortSignalI/OBT.656Display ModeY/C Di
Video Port Pin Mapping1-15OverviewSPRU6291.4.1 VDIN Bus Usage for Capture ModesThe alignment and usage of data on the VDIN bus depends on the capturem
Video Port Pin MappingOverview1-16 SPRU6291.4.2 VDOUT Data Bus Usage for Display ModesThe alignment and usage of data on the VDOUT bus depends on the
2-1Video PortThis chapter discusses the basic operation of the video port. Included is adiscussion of the sources and types of resets, interrupt opera
Reset OperationVideo Port2-2 SPRU6292.1 Reset OperationThe video port has several sources and types of resets. The actions performedby these resets an
Reset Operation2-3Video PortSPRU629If software sets the PEREN bit in PCR but the VPHLT bit in VPCTL remainsset:- VCLK1, VCLK2, and STCLK are enabled t
Reset OperationVideo Port2-4 SPRU629Once the port is configured and the VCEN bit is set, the setting of otherVCxCTL bits (except VCEN, RSTCH, and BLKC
Interrupt Operation2-5Video PortSPRU6292.2 Interrupt OperationThe video port can generate an interrupt to the DSP core after any of the follow-ing eve
DMA OperationVideo Port2-6 SPRU6292.3 DMA OperationThe video port uses up to three DMA events per channel for a total of sixpossible events. Each DMA
Trademarksiv SPRU629Code Composer Studio Application Programming Interface ReferenceGuide (literature number SPRU321) describes the Code ComposerStu
DMA Operation2-7Video PortSPRU629Figure 2–1. Capture DMA Event Generation Flow DiagramErrorOverflow errorYesOverflow errorFIFO overflow?NoYesYesCaptur
DMA OperationVideo Port2-8 SPRU629Because the capture FIFOs may hold multiple thresholds worth of data, aproblem arises at the boundaries between fiel
DMA Operation2-9Video PortSPRU629Figure 2–2. Display DMA Event Generation Flow DiagramStart of fieldFIFO emptyGenerate DMA event,new events disabledDi
DMA OperationVideo Port2-10 SPRU629A DMA event counter is used to track the number of DMA events generatedin each field as programmed in the VDDISPEVT
DMA Operation2-11Video PortSPRU629Similarly if a subhorizontal line length is desired (½ line, for example), then theline length and threshold must be
ClocksVideo Port2-12 SPRU6292.4 ClocksThe video port has three external clock inputs as shown in Table 2–1. Nosynchronization is required between the
Video Port Throughput and Latency2-13Video PortSPRU6292.5.2 FIFO SizeSome low-cost device implementations with narrow video ports width orrestricted t
Video Port Throughput and LatencyVideo Port2-14 SPRU629Table 2–2. Y/C Video Capture FIFO CapacitySample 8-Bit 10-Bit Dense 10-BitY Samples 2560 1920 1
Video Port Throughput and Latency2-15Video PortSPRU6292.6.2 Video Display ThroughputVideo display throughput may be calculated in a manner similar to
Video Port Control RegistersVideo Port2-16 SPRU629A DMA write throughput of at least 330 MBytes/s is required for the highestdisplay rate operation su
ContentsvContentsSPRU629Contents1 Overview 1-1. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Video Port Control Registers2-17Video PortSPRU6292.7.1 Video Port Control Register (VPCTL)The video port control register (VPCTL) determines the basic
Video Port Control RegistersVideo Port2-18 SPRU629Table 2–5. Video Port Control Register (VPCTL) Field Descriptions (Continued)Bit DescriptionValuesym
Video Port Control Registers2-19Video PortSPRU629Table 2–5. Video Port Control Register (VPCTL) Field Descriptions (Continued)Bit DescriptionValuesymv
Video Port Control RegistersVideo Port2-20 SPRU6292.7.2 Video Port Status Register (VPSTAT)The video port status register (VPSTAT) indicates the curre
Video Port Control Registers2-21Video PortSPRU6292.7.3 Video Port Interrupt Enable Register (VPIE)The video port interrupt enable register (VPIE) enab
Video Port Control RegistersVideo Port2-22 SPRU629Table 2–8. Video Port Interrupt Enable Register (VPIE) Field Descriptions (Continued)Bit Description
Video Port Control Registers2-23Video PortSPRU629Table 2–8. Video Port Interrupt Enable Register (VPIE) Field Descriptions (Continued)Bit DescriptionV
Video Port Control RegistersVideo Port2-24 SPRU6292.7.4 Video Port Interrupt Status Register (VPIS)The video port interrupt status register (VPIS) dis
Video Port Control Registers2-25Video PortSPRU629Table 2–9. Video Port Interrupt Status Register (VPIS) Field Descriptions (Continued)Bit DescriptionV
Video Port Control RegistersVideo Port2-26 SPRU629Table 2–9. Video Port Interrupt Status Register (VPIS) Field Descriptions (Continued)Bit Description
Contentsvi SPRU6292.6 Video Port Throughput and Latency 2-13. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2.6.
Video Port Control Registers2-27Video PortSPRU629Table 2–9. Video Port Interrupt Status Register (VPIS) Field Descriptions (Continued)Bit DescriptionV
Video Port Control RegistersVideo Port2-28 SPRU629Table 2–9. Video Port Interrupt Status Register (VPIS) Field Descriptions (Continued)Bit Description
Video Port Control Registers2-29Video PortSPRU629Table 2–9. Video Port Interrupt Status Register (VPIS) Field Descriptions (Continued)Bit DescriptionV
3-1Video Capture PortVideo capture works by sampling video data on the input pins and saving it tothe video port FIFO. When the amount of captured dat
Video Capture Mode SelectionVideo Capture Port3-2 SPRU6293.1 Video Capture Mode SelectionThe video capture module operates in one of nine modes as lis
BT.656 Video Capture Mode3-3Video Capture PortSPRU6293.2 BT.656 Video Capture ModeThe BT.656 capture mode captures 8-bit or 10-bit 4:2:2 luma and chro
BT.656 Video Capture ModeVideo Capture Port3-4 SPRU6293.2.2 BT.656 Timing Reference CodesFor standard digital video, there are two reference signals,
BT.656 Video Capture Mode3-5Video Capture PortSPRU629Bits P0, P1, P2, and P3 have different states depending on the state of bits F,V, and H as shown
BT.656 Video Capture ModeVideo Capture Port3-6 SPRU629Table 3–4. Error Correction by Protection Bits (Continued)ReceivedP3–P0 BitsReceived F, V, and H
BT.656 Video Capture Mode3-7Video Capture PortSPRU629Figure 3–1. Video Capture ParametersCapture ImageYstartXstartYstopXstopField 1Capture ImageYstart
ContentsviiContentsSPRU6293.8 TSI Capture Mode 3-37. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
BT.656 Video Capture ModeVideo Capture Port3-8 SPRU629For the BT.656 video capture mode, the FIFO buffer is divided into three sec-tions (three buffer
BT.656 Video Capture Mode3-9Video Capture PortSPRU6293.2.5 BT.656 FIFO PackingCaptured data is always packed into 64-bits before being written into th
BT.656 Video Capture ModeVideo Capture Port3-10 SPRU629The 10-bit BT.656 mode uses three FIFOs for color separation. Two samplesare packed into each w
BT.656 Video Capture Mode3-11Video Capture PortSPRU629The 10-bit BT.656 dense mode uses three FIFOs for color separation. Threesamples are packed into
Y/C Video Capture ModeVideo Capture Port3-12 SPRU6293.3 Y/C Video Capture ModeThe Y/C capture mode is similar to the BT.656 capture mode but captures
Y/C Video Capture Mode3-13Video Capture PortSPRU6293.3.3 Y/C Image Window and CaptureThe SDTV Y/C format (CCIR601) is an interlaced format consisting
Y/C Video Capture ModeVideo Capture Port3-14 SPRU6293.3.4 Y/C FIFO PackingCaptured data is always packed into 64 bits before being written into thecap
Y/C Video Capture Mode3-15Video Capture PortSPRU629The 10-bit Y/C mode uses three FIFOs for color separation. Two samples arepacked into each word wit
Y/C Video Capture ModeVideo Capture Port3-16 SPRU629The 10-bit Y/C dense mode uses three FIFOs for color separation. Three sam-ples are packed into ea
BT.656 and Y/C Mode Field and Frame Operation3-17Video Capture PortSPRU6293.4 BT.656 and Y/C Mode Field and Frame OperationBecause DMAs are used to tr
Contentsviii SPRU6294 Video Display Port 4-1. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
BT.656 and Y/C Mode Field and Frame OperationVideo Capture Port3-18 SPRU629Table 3–6. BT.656 and Y/C Mode Capture Operation VCxCTL BitCON FRAME CF2 C
BT.656 and Y/C Mode Field and Frame Operation3-19Video Capture PortSPRU629Table 3–6. BT.656 and Y/C Mode Capture Operation (Continued)VCxCTL BitCON Op
BT.656 and Y/C Mode Field and Frame OperationVideo Capture Port3-20 SPRU629Table 3–7. Vertical Synchronization ProgrammingVCxCTL BitVMode EXC VRST Ver
BT.656 and Y/C Mode Field and Frame Operation3-21Video Capture PortSPRU629Figure 3–8. VCOUNT Operation Example (EXC = 0)VF511LineVRST=010 5251262VCOUN
BT.656 and Y/C Mode Field and Frame OperationVideo Capture Port3-22 SPRU6293.4.3 Horizontal SynchronizationHorizontal synchronization determines when
BT.656 and Y/C Mode Field and Frame Operation3-23Video Capture PortSPRU629Figure 3–9. HCOUNT Operation Example (EXC = 0)VDIN[9–0]80.080.010.0FF.C00.00
BT.656 and Y/C Mode Field and Frame OperationVideo Capture Port3-24 SPRU6293.4.4 Field IdentificationIn order to properly synchronize to the source da
BT.656 and Y/C Mode Field and Frame Operation3-25Video Capture PortSPRU629The field detect method uses HYSNC and VSYNC based field detect logic.This i
Video Input FilteringVideo Capture Port3-26 SPRU629VCTL2 is a VSYNC (vertical sync) input, then a long field is always detected.(Even if VCYSTOPn is s
Video Input Filtering3-27Video Capture PortSPRU6293.5.2 Chrominance Resampling OperationChrominance resampling computes chrominance values at sample p
ContentsixContentsSPRU6294.12.6 Video Display Field 1 Vertical Blanking End Register (VDVBLKE1) 4-64. . . . . . . . 4.12.7 Video Display Field 2 Verti
Video Input FilteringVideo Capture Port3-28 SPRU629Figure 3–13. 1/2 Scaled Co-Sited FilteringYCbCr 4:2:2 co-sitedinput samples1/2 scaled co-sitedcaptu
Video Input Filtering3-29Video Capture PortSPRU6293.5.4 Edge Pixel ReplicationBecause the filters make use of preceding and trailing samples, filterin
Video Input FilteringVideo Capture Port3-30 SPRU629Figure 3–16 shows an example of a capture window that is smaller than theBT.656 active line. Sample
Ancillary Data Capture3-31Video Capture PortSPRU6293.6 Ancillary Data CaptureThe BT.656 and some Y/C specifications includes provision for carrying an
Raw Data Capture ModeVideo Capture Port3-32 SPRU6293.7 Raw Data Capture ModeIn the raw data capture mode, the data is sampled by the interface only wh
Raw Data Capture Mode3-33Video Capture PortSPRU629Table 3–11. Raw Data Mode Capture OperationVCxCTL BitCON FRAME CF2 CF1 Operation00 x x Noncontinuous
Raw Data Capture ModeVideo Capture Port3-34 SPRU629The 8-bit raw-data mode stores all data in a single FIFO. Four samples arepacked into each word as
Raw Data Capture Mode3-35Video Capture PortSPRU629The 10-bit dense raw data mode stores all data into a single FIFO. Three sam-ples are packed into ea
Raw Data Capture ModeVideo Capture Port3-36 SPRU629The 20-bit raw data mode stores all data into a single FIFO. One sample isplaced right justified in
TSI Capture Mode3-37Video Capture PortSPRU6293.8 TSI Capture ModeThe transport stream interface (TSI) capture mode captures MPEG-2 trans-port data.3.8
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