Texas-instruments TMS320C64x DSP Manuel d'utilisateur Page 24

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Video Port FIFO
1-7OverviewSPRU629
For 8/10-bit raw video, the FIFO is split into channel A and B, as shown in
Figure 13. Each FIFO is clocked independently with the channel A FIFO
receiving data from the VDIN[90] half of the bus and the channel B FIFO
receiving data from the VDIN[1910] half of the bus. Each channels FIFO has
a separate write pointer and read register (YSRCx). The FIFO configuration
is identical for TSI capture, but channel B is disabled.
Figure 13. 8/10-Bit Raw Video Capture and TSI Video Capture FIFO Configuration
VDIN[1910]
8/10
Buffer B (2560 bytes)
Capture FIFO B
YSRCB
64
VDIN[90]
8/10
Buffer A (2560 bytes)
Capture FIFO A
YSRCA
64
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