Texas-instruments Digital Signal Processor SM320F2812-HT Manuel d'utilisateur

SM320F2812-HTDigital Signal ProcessorData ManualPRODUCTION DATA information is current as of publication date.Products conform to specifications per t

SM320F2812-HTSGUS062B–JUNE 2009 – REVISED JUNE 2011www.ti.com10 List of Tables Copyright © 2009–2011, Texas Instruments Incorporated

SM320F2812-HTSGUS062B–JUNE 2009 – REVISED JUNE 2011www.ti.comTable 6-11 is also the STANDBY Mode Wake-Up Timing Requirements table.Table 6-11. STANDBY

tw(WAKE-INT)td(WAKE-STBY)td(IDLE−XCOH)32 SYSCLKOUT CyclesWake−upSignalX1/XCLKINXCLKOUT†STANDBY Normal ExecutionSTANDBYFlushing PipelineABCDEFDeviceSta

SM320F2812-HTSGUS062B–JUNE 2009 – REVISED JUNE 2011www.ti.comTable 6-12. HALT Mode Switching Characteristics(1)PARAMETER MIN TYP MAX UNITDelay time, I

SM320F2812-HTwww.ti.comSGUS062B– JUNE 2009– REVISED JUNE 2011A. IDLE instruction is executed to put the device into HALT mode.B. The PLL block respond

tw(PWM)td(PWM)XCOPWMxXCLKOUT(see Note A)XCLKOUT(see Note A)tw(TDIR)TDIRxSM320F2812-HTSGUS062B–JUNE 2009 – REVISED JUNE 2011www.ti.comTable 6-13. PWM S

XCLKOUTtd(XCOH-EVASOCL)EVASOCtw(EVASOCL)XCLKOUTtd(XCOH-EVBSOCL)EVBSOCtw(EVBSOCL)SM320F2812-HTwww.ti.comSGUS062B– JUNE 2009– REVISED JUNE 2011Table 6-1

PWM(see Note C)TxCTRIP, CxTRIP,PDPINTx(see Note B)XCLKOUT(see Note A)tw(PDP), tw(CxTRIP), tw(TxCTRIP)td(PDP-PWM)HZ, td(TRIP-PWM)HZXNMI, XINT1, XINT2tw

td(XCOH-GPO)GPIOXCLKOUTtr(GPO)tf(GPO)GPIOSignal1Sampling WindowQUALPRDOutput FromQualifier1 1 1 1 1 1 1 1 1 1 10 0 0 0 0 0 0 0 0 0SYSCLKOUTQUALPRD = 1

tc(SPC)+ SPI clock cycle time +LSPCLK4orLSPCLK(SPIBRR ) 1)+ tc(LCO)+ LSPCLK cycle timeGPIOxnXCLKOUTtw(GPI)(2)SM320F2812-HTSGUS062B–JUNE 2009 – REVISED

94SPISOMISPISIMOSPICLK (clock polarity = 1)SPICLK (clock polarity = 0)Master In DataMust Be ValidMaster Out Data Is Valid85321SPISTE(see Note A)SM320F

SM320F2812-HTwww.ti.comSGUS062B– JUNE 2009– REVISED JUNE 2011Digital Signal ProcessorCheck for Samples: SM320F2812-HT1 Features12• High-Performance St

tc(SPC)+ SPI clock cycle time +LSPCLK4orLSPCLK(SPIBRR ) 1)+ tc(LCO)+ LSPCLK cycle time(2)SM320F2812-HTSGUS062B–JUNE 2009 – REVISED JUNE 2011www.ti.com

Data Valid11SPISOMISPISIMOSPICLK (clock polarity = 1)SPICLK (clock polarity = 0)Master In DataMust Be ValidMaster Out Data Is Valid1761032SPISTE(see N

tc(SPC)+ SPI clock cycle time +LSPCLK4orLSPCLK(SPIBRR ) 1)+ tc(LCO)+ LSPCLK cycle time2015SPISIMOSPISOMISPICLK(clock polarity = 1)SPICLK(clock polarit

tc(SPC)+ SPI clock cycle time +LSPCLK4orLSPCLK(SPIBRR ) 1)+ tc(LCO)+ LSPCLK cycle time(2)SM320F2812-HTwww.ti.comSGUS062B– JUNE 2009– REVISED JUNE 2011

Data Valid22SPISIMOSPISOMISPICLK(clock polarity = 1)SPICLK(clock polarity = 0)SPISIMO DataMust Be ValidSPISOMI Data Is Valid211218171413SPISTE(see Not

SM320F2812-HTwww.ti.comSGUS062B– JUNE 2009– REVISED JUNE 2011LW ≥ tc(XTIM)These requirements result in the following XTIMING register configuration re

SM320F2812-HTSGUS062B–JUNE 2009 – REVISED JUNE 2011www.ti.com2. Active: AR ≥ 2 × tc(XTIM)AW ≥ 2 × tc(XTIM)NOTERestriction does not include external ha

XTIMING0XTIMING1XTIMING2XTIMING6XTIMING7XBANKLEAD/ACTIVE/TRAIL1†0XCLKOUT/2XTIMCLK1†0/2C28xCPUXINTCNF2(CLKMODE)XINTCNF2(XTIMCLK)†Default Value after re

SM320F2812-HTSGUS062B–JUNE 2009 – REVISED JUNE 2011www.ti.com6.22 XINTF Signal Alignment to XCLKOUTFor each XINTF access, the number of lead, active,

LeadActiveTrailDINtd(XCOHL-XRDL)td(XCOH-XA)td(XCOH-XZCSL)td(XCOHL-XRDH)th(XD)XRDtd(XCOHL-XZCSH)XCLKOUT=XTIMCLKXCLKOUT= 1/2 XTIMCLKXZCS0AND1, XZCS2,XZC

SM320F2812-HTxxxSGUS062B–JUNE 2009 – REVISED JUNE 2011www.ti.com1.1 SUPPORTS EXTREME TEMPERATURE APPLICATIONS• Controlled Baseline• One Assembly/Test

LeadActiveTrailtd(XCOH-XZCSL)td(XCOH-XA)td(XCOHL-XWEL)td(XCOHL-XWEH)td(XCOHL-XZCSH)ten(XD)XWELth(XD)XWEHtdis(XD)XRNWXCLKOUT=XTIMCLKXCLKOUT= 1/2 XTIMCL

SM320F2812-HTwww.ti.comSGUS062B– JUNE 2009– REVISED JUNE 2011XTIMING register parameters used for this example:XRDLEAD XRDACTIVE XRDTRAIL USEREADY X2T

SM320F2812-HTSGUS062B–JUNE 2009 – REVISED JUNE 2011www.ti.com6.25 External Interface Ready-on-Read Timing With One External Wait StateTable 6-37. Exte

LeadActiveTrailDINtd(XCOH-XZCSL)td(XCOH-XA)td(XCOHL-XRDL)td(XCOHL-XZCSH)td(XCOHL-XRDH)WS (Synch)XCLKOUT=XTIMCLKXCLKOUT= 1/2 XTIMCLKXZCS0AND1, XZCS2,XZ

tsu(XD)XRDLeadActiveTrailDINtd(XCOH-XZCSL)td(XCOH-XA)td(XCOHL-XRDL)td(XCOHL-XZCSH)td(XCOHL-XRDH)WS (Asynch)XCLKOUT=XTIMCLKXCLKOUT= 1/2 XTIMCLKXZCS0AND

SM320F2812-HTwww.ti.comSGUS062B– JUNE 2009– REVISED JUNE 20116.26 External Interface Ready-on-Write Timing With One External Wait StateTable 6-41. Ext

Lead 1ActiveTrailXCLKOUT = XTIMCLKXCLKOUT = 1/2 XTIMCLKXA[0:18]XD[0:15]XREADY(Synch)td(XCOHL-XWEL)td(XCOHL-XWEH)td(XCOHL-XZCSH)td(XCOH-XA)WS (Synch)XZ

Lead 1ActiveTrailXCLKOUT = XTIMCLKXCLKOUT = 1/2 XTIMCLKXA[0:18]XD[0:15]td(XCOHL-XWEH)td(XCOHL-XZCSH)td(XCOH-XA)WS (Asynch)XZCS0AND1, XZCS2,XZCS6AND7XR

SM320F2812-HTSGUS062B–JUNE 2009 – REVISED JUNE 2011www.ti.com6.27 XHOLD and XHOLDAf the HOLD mode bit is set while XHOLD and XHOLDA are both low (exte

XCLKOUT(/1 Mode)XHOLDXR/W,XZCS0AND1,XZCS2,XZCS6AND7XD[15:0] ValidXHOLDAtd(HL-Hiz)td(HH-HAH)High-ImpedanceXA[18:0]ValidValidHigh-Impedancetd(HH-BV)td(H

SM320F2812-HTwww.ti.comSGUS062B– JUNE 2009– REVISED JUNE 20112 IntroductionThis section provides a summary of the device features, lists the pin assig

SeeNote ASeeNoteBSM320F2812-HTSGUS062B–JUNE 2009 – REVISED JUNE 2011www.ti.comTable 6-45. XHOLD/XHOLDA Timing Requirements (XCLKOUT = 1/2 XTIMCLK)(

SM320F2812-HTwww.ti.comSGUS062B– JUNE 2009– REVISED JUNE 20116.29 On-Chip Analog-to-Digital Converter6.29.1 ADC Absolute Maximum RatingsVALUE(1)UNITVS

SM320F2812-HTSGUS062B–JUNE 2009 – REVISED JUNE 2011www.ti.com6.29.2 ADC Electrical Characteristics Over Recommended Operating ConditionsTable 6-46. DC

SM320F2812-HTwww.ti.comSGUS062B– JUNE 2009– REVISED JUNE 2011Table 6-47. AC Specifications(1) (2)TA= –55°C to 125°C TA= 220°CPARAMETER UNITMIN TYP MAX

acRsADCIN0Cp10 pFRon1 kΩ1.25 pFChSwitchTypical Values of the Input Circuit Components:Switch Resistance (Ron): 1 kΩSampling Capacitor (Ch): 1.25 pFPar

Analog Input onChannel Ax or BxADC ClockSample and HoldSH PulseSMODE Bittdschx_ntdschx_n+1Sample nSample n+1Sample n+2tSHADC Event Trigger fromEV or O

SM320F2812-HTSGUS062B–JUNE 2009 – REVISED JUNE 2011www.ti.comTable 6-50. Sequential Sampling Mode Timing(1)AT 25–MHz ADCSAMPLE n SAMPLE n + 1 CLOCK, R

Analog Input onChannel AxAnalog Input onChannel BvADC ClockSample and HoldSH PulsetSHtdschA0_ntdschB0_ntdschB0_n+1Sample nSample n+1Sample n+2tdschA0_

(SINAD 1.76)N6.02-=SM320F2812-HTSGUS062B–JUNE 2009 – REVISED JUNE 2011www.ti.com6.29.8 Definitions of Specifications and Terminology6.29.8.1 Integral

CLKG +CLKSRG(1 ) CLKGDV)(2) 2P = 1/CLKG in ns. CLKG is the output of sample rate generator mux.SM320F2812-HTwww.ti.comSGUS062B– JUNE 2009– REVISED JUN

SM320F2812-HTSGUS062B–JUNE 2009 – REVISED JUNE 2011www.ti.com2.3 Die LayoutThe SM320F2812 die layout is shown in Figure 2-1. See Table 2-3 for a descr

SM320F2812-HTSGUS062B–JUNE 2009 – REVISED JUNE 2011www.ti.comTable 6-53. McBSP Switching Characteristics(1) (2) (3)NO. PARAMETER MIN MAX UNITM1 tc(CKR

(n−2)Bit (n−1)(n−3)(n−2)Bit (n−1)(n−4)(n−3)(n−2)Bit (n−1)M18M17M18M17M17M18M16M15M4M4M14M13M3, M12M1, M11M2, M12(RDATDLY= 10b)DR(RDATDLY= 01b)DR(RDATD

Bit 0 Bit(n-1) (n-2) (n-3) (n-4)Bit 0 Bit(n-1) (n-2) (n-3) (n-4)CLKXFSXDXM30M31DRM28M24M29M25LSBMSBM32M33SM320F2812-HTSGUS062B–JUNE 2009 – REVISED JUN

Bit 0 Bit(n-1) (n-2) (n-3) (n-4)Bit 0 Bit(n-1) (n-2) (n-3) (n-4)CLKXFSXDXDRM35M37M40M39M38M34LSBMSBM41M42SM320F2812-HTwww.ti.comSGUS062B– JUNE 2009– R

M51M50M47Bit 0 Bit(n-1) (n-2) (n-3) (n-4)Bit 0 Bit(n-1) (n-2) (n-3) (n-4)CLKXFSXDXDRM44M48M49M43LSBMSBM52SM320F2812-HTSGUS062B–JUNE 2009 – REVISED JUN

Bit 0 Bit(n-1) (n-2) (n-3) (n-4)Bit 0 Bit(n-1) (n-2) (n-3) (n-4)CLKXFSXDXDRM54M58M56M53M55M59M57LSBMSBM60M61SM320F2812-HTwww.ti.comSGUS062B– JUNE 2009

SM320F2812-HTSGUS062B–JUNE 2009 – REVISED JUNE 2011www.ti.com6.31 Flash Timing6.31.1 Recommended Operating ConditionsTable 6-62. Flash Endurance Timin

SM320F2812-HTwww.ti.comSGUS062B– JUNE 2009– REVISED JUNE 2011Table 6-65. Minimum Required Wait-States at Different Frequencies(1)SYSCLKOUT (MHz) SYSCL

SM320F2812-HTSGUS062B–JUNE 2009 – REVISED JUNE 2011www.ti.com7 Mechanical DataThe following mechanical package diagram(s) reflect the most current rel

SM320F2812-HTwww.ti.comSGUS062B– JUNE 2009– REVISED JUNE 2011Revision HistoryNOTE: Page numbers for previous revisions may differ from page numbers in

VDDAIO1130172ADCINB0ADCINB1ADCINB2ADCINB3ADCINB4ADCINB5ADCINB6ADCINB7ADCREFMADCREFPAVSSREFBGAVDDREFBGVDDA1VSSA1ADCRESEXTMCXMP/XA[0]MDRAXD[0]MDXAVDDXD[

PACKAGE OPTION ADDENDUMwww.ti.com24-Sep-2012Addendum-Page 1PACKAGING INFORMATIONOrderable DeviceStatus (1)Package Type PackageDrawingPins Package QtyE

PACKAGE OPTION ADDENDUMwww.ti.com24-Sep-2012Addendum-Page 2•Catalog - TI's standard catalog product•Enhanced Product - Supports Defense, Aerospac

IMPORTANT NOTICETexas Instruments Incorporated and its subsidiaries (TI) reserve the right to make corrections, enhancements, improvements and otherch

SM320F2812-HTSGUS062B–JUNE 2009 – REVISED JUNE 2011www.ti.com2.5 Signal DescriptionsTable 2-3 specifies the signals on the F2812 device. All digital i

SM320F2812-HTwww.ti.comSGUS062B– JUNE 2009– REVISED JUNE 2011Table 2-3. Signal Descriptions(1)(continued)PIN NO.DIE PAD DIE PADDIE PADNAME X-CENTER Y-

SM320F2812-HTSGUS062B–JUNE 2009 – REVISED JUNE 2011www.ti.comTable 2-3. Signal Descriptions(1)(continued)PIN NO.DIE PAD DIE PADDIE PADNAME X-CENTER Y-

SM320F2812-HTwww.ti.comSGUS062B– JUNE 2009– REVISED JUNE 2011Table 2-3. Signal Descriptions(1)(continued)PIN NO.DIE PAD DIE PADDIE PADNAME X-CENTER Y-

SM320F2812-HTSGUS062B–JUNE 2009 – REVISED JUNE 2011www.ti.comContents1 Features ...

SM320F2812-HTSGUS062B–JUNE 2009 – REVISED JUNE 2011www.ti.comTable 2-3. Signal Descriptions(1)(continued)PIN NO.DIE PAD DIE PADDIE PADNAME X-CENTER Y-

SM320F2812-HTwww.ti.comSGUS062B– JUNE 2009– REVISED JUNE 2011Table 2-3. Signal Descriptions(1)(continued)PIN NO.DIE PAD DIE PADDIE PADNAME X-CENTER Y-

SM320F2812-HTSGUS062B–JUNE 2009 – REVISED JUNE 2011www.ti.comSignal Descriptions (Continued)(1)PIN NO.PERIPHERAL DIE PAD DIE PADGPIO DIE PAD NO. I/O/Z

SM320F2812-HTwww.ti.comSGUS062B– JUNE 2009– REVISED JUNE 2011Signal Descriptions (Continued)(1)(continued)PIN NO.PERIPHERAL DIE PAD DIE PADGPIO DIE PA

SM320F2812-HTSGUS062B–JUNE 2009 – REVISED JUNE 2011www.ti.comSignal Descriptions (Continued)(1)(continued)PIN NO.PERIPHERAL DIE PAD DIE PADGPIO DIE PA

M0 SARAM1K x 16CPU-Timer 0CPU-Timer 1INT[12:1]CLKINReal-Time JTAGCPU-Timer 2Peripheral BusC28x CPUH0 SARAM8K ⋅ 16INT14NMIINT13Memory BusM1 SARAM1K x 1

BlockStart AddressLow 64K(24x/240x Equivalent Data Space)0x00 0000M0 Vector − RAM (32 × 32)(Enabled if VMAP = 0)Data Space Prog SpaceM0 SARAM (1K × 16

SM320F2812-HTwww.ti.comSGUS062B– JUNE 2009– REVISED JUNE 2011Table 3-1. Addresses of Flash Sectors in F2812ADDRESS RANGE PROGRAM AND DATA SPACE0x3D 80

SM320F2812-HTSGUS062B–JUNE 2009 – REVISED JUNE 2011www.ti.commemory such that the vector table is fetched externally. The Boot ROM is disabled in this

SM320F2812-HTwww.ti.comSGUS062B– JUNE 2009– REVISED JUNE 20113.2 Brief Descriptions3.2.1 C28x CPUThe C28x™ DSP generation is the newest member of the

SM320F2812-HTwww.ti.comSGUS062B– JUNE 2009– REVISED JUNE 20114 Peripherals ...

SM320F2812-HTSGUS062B–JUNE 2009 – REVISED JUNE 2011www.ti.comsingle step through non-time critical code while enabling time-critical interrupts to be

SM320F2812-HTwww.ti.comSGUS062B– JUNE 2009– REVISED JUNE 2011Table 3-3. Boot Mode SelectionGPIOF4 GPIOF12 GPIOF3 GPIOF2BOOT MODE SELECTED(1)(SCITXDA)

SM320F2812-HTSGUS062B–JUNE 2009 – REVISED JUNE 2011www.ti.comIN NO EVENT SHALL TI BE LIABLE FOR ANY CONSEQUENTIAL, SPECIAL,INDIRECT, INCIDENTAL, OR PU

SM320F2812-HTwww.ti.comSGUS062B– JUNE 2009– REVISED JUNE 2011HALT: Turn off oscillator. This mode basically shuts down the device and places it in the

SM320F2812-HTSGUS062B–JUNE 2009 – REVISED JUNE 2011www.ti.com3.2.20 Serial Port PeripheralsThe F2812 supports the following serial communication perip

SM320F2812-HTwww.ti.comSGUS062B– JUNE 2009– REVISED JUNE 2011Table 3-4. Peripheral Frame 0 Registers(1)NAME ADDRESS RANGE SIZE (×16) ACCESS TYPE(2)0x0

SM320F2812-HTSGUS062B–JUNE 2009 – REVISED JUNE 2011www.ti.comTable 3-6. Peripheral Frame 2 Registers(1)NAME ADDRESS RANGE SIZE (×16) ACCESS TYPE0x00 7

SM320F2812-HTwww.ti.comSGUS062B– JUNE 2009– REVISED JUNE 20113.4 Device Emulation RegistersThese registers are used to control the protection mode of

XD(15:0)XA(18:0)XZCS6XZCS7XZCS6AND7XZCS2XWEXR/WXREADYXMP/MCXHOLDXHOLDAXCLKOUTXRDXINTF Zone 0(8K × 16)XINTF Zone 1(8K × 16)XINTF Zone 6(512K × 16)XINTF

SM320F2812-HTwww.ti.comSGUS062B– JUNE 2009– REVISED JUNE 2011The operation and timing of the external interface, can be controlled by the registers li

SM320F2812-HTSGUS062B–JUNE 2009 – REVISED JUNE 2011www.ti.com6.21 External Interface (XINTF) Timing ...

C28x CPUPIETIMER 2 (for RTOS)TIMER 0WatchdogPeripherals (SPI, SCI, McBSP, CAN, EV, ADC)(41 Interrupts)96 Interrupts†TINT0Interrupt ControlXNMICR(15:0)

INT12MUXINT11INT2INT1CPU(Enable)(Flag)INTxINTx.8PIEIERx(8:1) PIEIFRx(8:1)MUXINTx.7INTx.6INTx.5INTx.4INTx.3INTx.2INTx.1FromPeripherals orExternalInterr

SM320F2812-HTSGUS062B–JUNE 2009 – REVISED JUNE 2011www.ti.comTable 3-11. PIE Configuration and Control Registers(1)NAME ADDRESS SIZE (×16) DESCRIPTION

SM320F2812-HTwww.ti.comSGUS062B– JUNE 2009– REVISED JUNE 20113.6.1 External InterruptsTable 3-12. External Interrupts RegistersNAME ADDRESS SIZE (×16)

SeeNote ASM320F2812-HTSGUS062B–JUNE 2009 – REVISED JUNE 2011www.ti.com3.7 System ControlThis section describes the F2812 oscillator, PLL and clocking

SM320F2812-HTwww.ti.comSGUS062B– JUNE 2009– REVISED JUNE 2011The PLL, clocking, watchdog, and low-power modes are controlled by the registers listed i

X2X1/XCLKINOn-ChipOscillator(OSC)PLLBypass/2XF_XPLLDISOSCCLK (PLL Disabled)LatchXPLLDISXRSPLL4-Bit PLL SelectSYSCLKOUT10CLKINCPU4-Bit PLL SelectXCLKIN

External Clock Signal (Toggling 0−VDD)Cb1(see Note A)X2X1/XCLKIN X1/XCLKIN X2CrystalCb2(see Note A)(a) (b)NCSM320F2812-HTwww.ti.comSGUS062B– JUNE 2009

/512OSCCLKWDCR (WDPS(2:0))WDCLKWDCNTR(7:0)WDKEY(7:0)Bad KeyGood Key1 0 1WDCR (WDCHK(2:0))BadWDCHKKeyWDCR (WDDIS)Clear CounterSCSR (WDENINT)WatchdogPre

SM320F2812-HTwww.ti.comSGUS062B– JUNE 2009– REVISED JUNE 20113.12 Low-Power Modes BlockThe low-power modes on the F2812 are similar to the 240x device

SM320F2812-HTwww.ti.comSGUS062B– JUNE 2009– REVISED JUNE 2011List of Figures2-1 SM320F2812 Die Layout...

BorrowResetTimer ReloadSYSCLKOUTTCR.4(Timer Start Status)TINT16-Bit Timer Divide-Down TDDRH:TDDR32-Bit Timer PeriodPRDH:PRD32-Bit CounterTIMH:TIM16-Bi

INT1toINT12INT14C28xTINT2TINT0PIECPU-TIMER 0CPU-TIMER 2 (Reserved for TI system functions)INT13TINT1CPU-TIMER 1 (Reserved for TI system functions)XINT

SM320F2812-HTSGUS062B–JUNE 2009 – REVISED JUNE 2011www.ti.comTable 4-1. CPU-Timers 0, 1, 2 Configuration and Control RegistersNAME ADDRESS SIZE (×16)

SM320F2812-HTwww.ti.comSGUS062B– JUNE 2009– REVISED JUNE 20114.2 Event Manager Modules (EVA, EVB)The event-manager modules include general-purpose (GP

SM320F2812-HTSGUS062B–JUNE 2009 – REVISED JUNE 2011www.ti.comTable 4-3. EVA Registers(1)NAME ADDRESS SIZE (×16) DESCRIPTIONGPTCONA 0x00 7400 1 GP Time

GPTCONA(12:4), CAPCONA(8), EXTCONA[0]EVATO ADC (Internal)Timer 1 CompareOutputLogicT1PWM_T1CMPGPTCONA(1,0)T1CON(1)GP Timer 1TCLKINAPrescalerHSPCLKT1CO

SM320F2812-HTSGUS062B–JUNE 2009 – REVISED JUNE 2011www.ti.com4.2.1 General-Purpose (GP) TimersThere are two GP timers. The GP timer x (x = 1 or 2 for

SM320F2812-HTwww.ti.comSGUS062B– JUNE 2009– REVISED JUNE 20114.2.6 PWM CharacteristicsCharacteristics of the PWMs are as follows:• 16-bit registers• W

Input Analog Voltage ADCLO4096 ,3-´SM320F2812-HTSGUS062B–JUNE 2009 – REVISED JUNE 2011www.ti.com4.3 Enhanced Analog-to-Digital Converter (ADC) ModuleA

Result RegistersEVBS/WADCSOCEVAS/WSequencer 2Sequencer 1SOCSOCADC Control Registers70B7h70B0h70AFh70A8hResult Reg 15Result Reg 8Result Reg 7Result Reg

SM320F2812-HTSGUS062B–JUNE 2009 – REVISED JUNE 2011www.ti.com6-24 SPI Master Mode External Timing (Clock Phase = 0) ...

ADCINA[7:0]ADCINB[7:0]ADCLOADCBGREFIN†ADC External Current Bias Resistor ADCRESEXTADCREFPVDDA1VDDA2VSSA1VSSA2AVDDREFBGAVSSREFBGVDDAIOVSSAIOVDD1VSS1Tes

ADCINA[7:0]ADCINB[7:0]ADCLOADCBGREFINADC External Current Bias Resistor ADCRESEXTADCREFPVDDA1VDDA2VSSA1VSSA2AVDDREFBGAVSSREFBGVDDAIOVSSAIOVDD1VSS1Test

SM320F2812-HTSGUS062B–JUNE 2009 – REVISED JUNE 2011www.ti.comThe ADC operation is configured, controlled, and monitored by the registers listed in Tab

SM320F2812-HTwww.ti.comSGUS062B– JUNE 2009– REVISED JUNE 20114.4 Enhanced Controller Area Network (eCAN) ModuleThe CAN module has the following featur

Mailbox RAM(512 Bytes)32-Message Mailboxof 4 × 32-Bit WordsMemory ManagementUnitCPU Interface,Receive Control Unit,Timer Management UniteCAN Memory(51

Mailbox Enable − CANMEMailbox Direction − CANMDTransmission Request Set − CANTRSTransmission Request Reset − CANTRRTransmission Acknowledge − CANTAAbo

SM320F2812-HTSGUS062B–JUNE 2009 – REVISED JUNE 2011www.ti.comThe CAN registers listed in Table 4-6 are used by the CPU to configure and control the CA

CLKSRGMcBSP clock rate CLKG ,1 CLKGDIV= =+SM320F2812-HTwww.ti.comSGUS062B– JUNE 2009– REVISED JUNE 20114.5 Multichannel Buffered Serial Port (McBSP) M

McBSP ReceiveInterrupt Select LogicDXDRExpand LogicDRR1 Receive BufferRX FIFOInterruptDRR2 Receive BufferRX FIFO RegistersRBR1 RegisterRBR2 RegisterMc

SM320F2812-HTwww.ti.comSGUS062B– JUNE 2009– REVISED JUNE 2011Table 4-7 provides a summary of the McBSP registers.Table 4-7. McBSP Register SummaryADDR

SM320F2812-HTwww.ti.comSGUS062B– JUNE 2009– REVISED JUNE 2011List of Tables2-1 Hardware Features...

SM320F2812-HTSGUS062B–JUNE 2009 – REVISED JUNE 2011www.ti.comTable 4-7. McBSP Register Summary (continued)ADDRESS TYPE RESET VALUENAME DESCRIPTION0x00

LSPCLK,(BRR 1) 8+ ·LSPCLK,166150 MHzMax bit rate 9.375 10 b / s2 8= = ´´SM320F2812-HTwww.ti.comSGUS062B– JUNE 2009– REVISED JUNE 20114.6 Serial Commun

SM320F2812-HTSGUS062B–JUNE 2009 – REVISED JUNE 2011www.ti.comNOTEAll registers in this module are 8-bit registers that are connected to Peripheral Fra

TX FIFO _0LSPCLKWUTFrame Format and ModeEven/Odd EnableParitySCI RX Interrupt select logicBRKDTRXRDYSCIRXST.6SCICTL1.38SCICTL2.1RX/BK INT ENASCIRXDSCI

LSPCLK,(SPIBRR 1)+LSPCLK,4SM320F2812-HTSGUS062B–JUNE 2009 – REVISED JUNE 2011www.ti.com4.7 Serial Peripheral Interface (SPI) ModuleThe F2812 device in

SM320F2812-HTwww.ti.comSGUS062B– JUNE 2009– REVISED JUNE 2011Enhanced feature:• 16-level transmit/receive FIFO• Delayed transmit controlThe SPI port o

SSPICTL.0SPI INT FLAGSPI INTENASPISTS.6SClockPolarityTalkLSPCLK456 123 00123SPI Bit RateState ControlSPIRXBUFBuffer RegisterClockPhaseReceiverOverrun

SM320F2812-HTwww.ti.comSGUS062B– JUNE 2009– REVISED JUNE 20114.8 GPIO MUXThe GPIO Mux registers are used to select the operation of shared pins on the

SM320F2812-HTSGUS062B–JUNE 2009 – REVISED JUNE 2011www.ti.comTable 4-12. GPIO Data Registers(1) (2)NAME ADDRESS SIZE (×16) REGISTER DESCRIPTIONGPADAT

Peripheral I/OMUX0 1MUX10PINInternal (Pullup or Pulldown)Digital I/OXRSHigh-ImpedanceEnable (1)High-ImpedanceControlGPxDIRRegister BitGPxMUXRegister B

SM320F2812-HTSGUS062B–JUNE 2009 – REVISED JUNE 2011www.ti.com6-17 Interrupt Switching Characteristics ...

SM320F2812-HTSGUS062B–JUNE 2009 – REVISED JUNE 2011www.ti.com5 Development SupportTexas Instruments (TI) offers an extensive line of development tools

PREFIXSM 320 F 2812 HFGTMX = experimental deviceTMP = prototype deviceTMS = qualified deviceSM = commercial processingSMJ = MIL-PRF-38535 (QML)DEVICE

SM320F2812-HTSGUS062B–JUNE 2009 – REVISED JUNE 2011www.ti.comTMS320x281x, 280x Enhanced Controller Area Network (eCAN) Reference Guide (SPRU074)descri

SM320F2812-HTwww.ti.comSGUS062B– JUNE 2009– REVISED JUNE 2011To send comments regarding this TMS320F281x/TMS320C281x data manual (SPRS174), use thecom

SM320F2812-HTSGUS062B–JUNE 2009 – REVISED JUNE 2011www.ti.com6 Electrical SpecificationsThis section provides the absolute maximum ratings and the rec

SM320F2812-HTwww.ti.comSGUS062B– JUNE 2009– REVISED JUNE 20116.2 Recommended Operating ConditionsSee(1)MIN NOM MAX UNITVDDIODevice supply voltage, I/O

1.00E+061.00E+051.00E+041.00E+031.00E+0270 150 200 220Die Junction Temperature (°C)HoursSM320F2812-HTSGUS062B–JUNE 2009 – REVISED JUNE 2011www.ti.comF

SM320F2812-HTwww.ti.comSGUS062B– JUNE 2009– REVISED JUNE 20116.4 Current Consumption by Power-Supply Pins Over Recommended OperatingConditions During

0501001502002500 20 40 60 80 100 120 140 160SYSCLKOUT (MHz)IDDIDDIOIDD3VFL IDDA Total 3.3−V currentCurrent (mA)01002003004005006007000 20 40 60 80 10

SM320F2812-HTwww.ti.comSGUS062B– JUNE 2009– REVISED JUNE 20116.6 Reducing Current Consumption28x DSPs incorporate a unique method to reduce the device

SM320F2812-HTwww.ti.comSGUS062B– JUNE 2009– REVISED JUNE 20116-65 Minimum Required Wait-States at Different Frequencies ...

SeeFigure6-8,SM320F2812-HTSGUS062B–JUNE 2009 – REVISED JUNE 2011www.ti.comxxxNOTEThe GPIO pins are undefined until VDD= 1 V and VDDIO= 2.5 V.Figure

0.4 V (VOL)20%2.4 V (VOH)80%0.8 V (VIL)10%2.0 V (VIH)90%SM320F2812-HTwww.ti.comSGUS062B– JUNE 2009– REVISED JUNE 20116.8 Signal Transition LevelsN

Transmission Line4.0 pF 1.85 pFZ0 = 50 Ω(see note)Tester Pin ElectronicsData Sheet Timing Reference PointOutputUnderTestNOTE: The data sheet provides

SM320F2812-HTwww.ti.comSGUS062B– JUNE 2009– REVISED JUNE 20116.12 Device Clock TableThis section provides the timing requirements and switching charac

SM320F2812-HTSGUS062B–JUNE 2009 – REVISED JUNE 2011www.ti.comTable 6-5. XCLKIN Timing Requirements – PLL Bypassed or Enabled(1)NO. MIN MAX UNITC8 tc(C

SeeNote ASeeNoteBSM320F2812-HTwww.ti.comSGUS062B– JUNE 2009– REVISED JUNE 2011A. The relationship of XCLKIN to XCLKOUT depends on the divide factor

tw(RSL1)th(XPLLDIS)th(XMP/MC)th(boot-mode)(See Note D)VDDIO, VDD3VFLVDDAn, VDDAIO(3.3 V) (See Note B)XCLKIN2.5 V0.3 VX1XRSXF/XPLLDISXMP/MCBoot-Mode Pi

tw(RSL)th(XPLLDIS)th(XMP/MC)tOSCSTVDDIO, VDD3VFLVDDAn, VDDAIO(3.3 V)XCLKINX1XRSXF/XPLLDISXMP/MCVDD, VDD1 (1.8 V (or1.9 V))I/O PinsXPLLDIS SamplingAddr

XCLKIN/8(XCLKIN * 5)th(XPLLDIS)th(XMP/MC)th(boot-mode) (see Note A)tw(RSL2)XCLKINX1XRSXF/XPLLDISXMP/MCBoot-Mode PinsXCLKOUTI/O PinsAddress/Data/Contro

WAKE INT(see Note B)XCLKOUT(see Note A)A0−A15td(WAKE−IDLE)tw(WAKE−INT)SM320F2812-HTwww.ti.comSGUS062B– JUNE 2009– REVISED JUNE 20116.15 Low-Power Mode