Texas-instruments TMS320C6454 Manuel d'utilisateur télécharger pdf (Page 135)

www.ti.com

PRODUCT PREVIEW

TMS320C6454

Fixed-Point Digital Signal Processor

SPRS311A – APRIL 2006 – REVISED DECEMBER 2006

7.7.3.9 PLLDIV Ratio Change Status Register

Whenever a different ratio is written to the PLLDIV n registers, the PLLCTRL flags the change in the

PLLDIV ratio change status registers (DCHANGE). During the GO operation, the PLL controller will only

change the divide ratio of the SYSCLKs with the bit set in DCHANGE. Note that changed clocks will be

automatically aligned to other clocks. The PLLDIV divider ratio change status register is shown in

Figure 7-19 and described in Table 7-27 .

31 16

Reserved

R-0

15 5 4 3 2 0

Reserved SYS5 SYS4 Reserved

R-0 R-0 R-0 R-0

LEGEND: R/W = Read/Write; R = Read only; - n = value after reset

Figure 7-19. PLLDIV Divider Ratio Change Status Register (DCHANGE) [Hex Address: 029A 0144]

Table 7-27. PLLDIV Divider Ratio Change Status Register (DCHANGE) Field Descriptions

Bit Field Value Description

31:5 Reserved 0 Reserved. The reserved bit location is always read as 0. A value written to this field has no effect.

4 SYS5 Identifies when the SYSCLK5 divide ratio has been modified.

0 SYSCLK5 ratio has not been modified. When GOSET is set, SYSCLK5 will not be affected.

1 SYSCLK5 ratio has been modified. When GOSET is set, SYSCLK5 will change to the new ratio.

3 SYS4 Identifies when the SYSCLK4 divide ratio has been modified.

0 SYSCLK4 ratio has not been modified. When GOSET is set, SYSCLK4 will not be affected.

1 SYSCLK4 ratio has been modified. When GOSET is set, SYSCLK4 will change to the new ratio.

2:0 Reserved 0 Reserved. The reserved bit location is always read as 0. A value written to this field has no effect.

Submit Documentation Feedback C64x+ Peripheral Information and Electrical Specifications 135

1 2 ... 130 131 132 133 134 135 136 137 138 139 140 ... 224 225

Pas de commentaire

Texas-instruments TMS320C6454 Manuel d'utilisateur Page 135