Texas Instruments TMS320TCI648x Manuel d'utilisateur

TMS320TCI648x Serial RapidIO (SRIO)User's GuideLiterature Number: SPRUE13ASeptember 2006

List of Tables1 TI Devices Supported By This Document ... 202 Registers Ch

www.ti.com4.8 Interrupt HandlingInterrupt Conditionsimmediately starts down-counting each time the CPU writes these registers. When the rate control c

www.ti.comInterrupt ConditionsInterrupt Handlertemp1 = SRIO_REGS->TX_CPPI_ICSR;if ((temp1 & 0x00000001) == 0x00000001){SRIO_REGS->Queue0_TXD

www.ti.com5 SRIO Registers5.1 IntroductionSRIO RegistersTable 40 lists the names and address offsets of the memory-mapped registers for the Serial Rap

www.ti.comSRIO RegistersTable 40. Serial RapidIO (SRIO) Registers (continued)Offset Acronym Register Description Section011Ch SERDES_CFGTX3_CNTL SERDE

www.ti.comSRIO RegistersTable 40. Serial RapidIO (SRIO) Registers (continued)Offset Acronym Register Description Section030Ch INTDST3_DECODE INTDST In

www.ti.comSRIO RegistersTable 40. Serial RapidIO (SRIO) Registers (continued)Offset Acronym Register Description Section0504h QUEUE1_TXDMA_HDP Queue T

www.ti.comSRIO RegistersTable 40. Serial RapidIO (SRIO) Registers (continued)Offset Acronym Register Description Section063Ch QUEUE15_RXDMA_HDP Queue

www.ti.comSRIO RegistersTable 40. Serial RapidIO (SRIO) Registers (continued)Offset Acronym Register Description Section0838h RXU_MAP_L7 MailBox-to-Qu

www.ti.comSRIO RegistersTable 40. Serial RapidIO (SRIO) Registers (continued)Offset Acronym Register Description Section08F0h RXU_MAP_L30 MailBox-to-Q

www.ti.comSRIO RegistersTable 40. Serial RapidIO (SRIO) Registers (continued)Offset Acronym Register Description Section117Ch SP1_CTL Port 1 Control C

50 RapidIO DEVICEID1 Register (DEVICEID_REG1) Field Descriptions ... 12151 RapidIO DEVICEID2 Register (DEVICE

www.ti.comSRIO RegistersTable 40. Serial RapidIO (SRIO) Registers (continued)Offset Acronym Register Description Section2100h SP3_ERR_DET Port 3 Error

www.ti.com5.2 Peripheral Identification Register (PID)SRIO RegistersThe peripheral identification register (PID) is a read-only register that contains

www.ti.com5.3 Peripheral Control Register (PCR)SRIO RegistersThe peripheral control register (PCR) contains a bit that enables or disables data flow i

www.ti.com5.4 Peripheral Settings Control Register (PER_SET_CNTL)SRIO RegistersThe peripheral settings control register (PER_SET_CNTL) is shown in Fig

www.ti.comSRIO RegistersTable 43. Peripheral Settings Control Register (PER_SET_CNTL) Field Descriptions (continued)Bit Field Value Description17–15 T

www.ti.comSRIO RegistersTable 43. Peripheral Settings Control Register (PER_SET_CNTL) Field Descriptions (continued)Bit Field Value Description3 ENPLL

www.ti.com5.5 Peripheral Global Enable Register (GBL_EN)SRIO RegistersGBL_EN is implemented with a single enable bit for the entire SRIO peripheral. T

www.ti.com5.6 Peripheral Global Enable Status Register (GBL_EN_STAT)SRIO RegistersThe peripheral global enable status register (GBL_EN_STAT) is shown

www.ti.comSRIO RegistersTable 45. Peripheral Global Enable Status Register (GBL_EN_STAT) Field Descriptions (continued)Bit Field Value Description1 BL

www.ti.com5.7 Block n Enable Register (BLK n_EN)SRIO RegistersThere are nine of these registers, one for each of nine logical blocks in the peripheral

99 LSU n_REG6 Registers and the Associated LSUs ... 161100 LSU n Control Register 6 (L

www.ti.com5.8 Block n Enable Status Register (BLK n_EN_STAT)SRIO RegistersThere are nine of these registers, one for each of nine logical blocks in th

www.ti.com5.9 RapidIO DEVICEID1 Register (DEVICEID_REG1)SRIO RegistersThe RapidIO DEVICEID1 register (DEVICEID_REG1) is shown in Figure 70 and describ

www.ti.com5.10 RapidIO DEVICEID2 Register (DEVICEID_REG2)SRIO RegistersThe RapidIO DEVICEID2 register (DEVICEID_REG2 is shown in Figure 71 and describ

www.ti.com5.11 Packet Forwarding Register n for 16-Bit Device IDs (PF_16B_CNTL n)SRIO RegistersThere are four of these registers (see Table 52 ). The

www.ti.com5.12 Packet Forwarding Register n for 8-Bit Device IDs (PF_8B_CNTL n)SRIO RegistersThere are four of these registers (see Table 54 ). The ge

www.ti.com5.13 SERDES Receive Channel Configuration Register n (SERDES_CFGRX n_CNTL)SRIO RegistersThere are four of these registers, to support four p

www.ti.comSRIO RegistersTable 57. SERDES Receive Channel Configuration Register n (SERDES_CFGRX n_CNTL) FieldDescriptions (continued)Bit Field Value D

www.ti.comSRIO RegistersTable 58. EQ Bits (continued)CFGRX[22–19] Low Freq Gain Zero Freq (at e28(min))1000b Adaptive 1084MHz1001b 805MHz1010b 573MHz1

www.ti.com5.14 SERDES Transmit Channel Configuration Register n (SERDES_CFGTX n_CNTL)SRIO RegistersThere are four of these registers, to support four

www.ti.comSRIO RegistersTable 60. SERDES Transmit Channel Configuration Register n (SERDES_CFGTX n_CNTL) FieldDescriptions (continued)Bit Field Value

150 Error Reporting Block Header Register (ERR_RPT_BH) Field Descriptions ... 209151 Logical/Transport Layer Error D

www.ti.com5.15 SERDES Macro Configuration Register n (SERDES_CFG n_CNTL)SRIO RegistersThere are four of these registers, to support four ports (see Ta

www.ti.comSRIO RegistersTable 64. SERDES Macro Configuration Register n (SERDES_CFG n_CNTL) Field Descriptions(continued)Bit Field Value Description5–

www.ti.com5.16 DOORBELL n Interrupt Condition Status Register (DOORBELL n_ICSR)SRIO RegistersThe four doorbell interrupts are mapped to these register

www.ti.com5.17 DOORBELL n Interrupt Condition Clear Register (DOORBELL n_ICCR)SRIO RegistersThe four doorbells interrupts that are mapped are cleared

www.ti.com5.18 RX CPPI Interrupt Status Register (RX_CPPI_ICSR)SRIO RegistersThe bits in this register indicate any active interrupt requests from RX

www.ti.com5.19 RX CPPI Interrupt Clear Register (RX_CPPI_ICCR)SRIO RegistersThis register is used to clear bits in RX_CPPI_ICSR to acknowledge interru

www.ti.com5.20 TX CPPI Interrupt Status Register (TX_CPPI_ICSR)SRIO RegistersThe bits in this register indicate any active interrupt requests from TX

www.ti.com5.21 TX CPPI Interrupt Clear Register (TX_CPPI_ICCR)SRIO RegistersThis register is used to clear bits in TX_CPPI_ICSR to acknowledge interru

www.ti.com5.22 LSU Interrupt Condition Status Register (LSU_ICSR)SRIO RegistersEach of the status bits in this register indicates the occurrence of a

www.ti.comSRIO RegistersTable 73. LSU Interrupt Condition Status Register (LSU_ICSR) Field Descriptions (continued)Bit Field Value Description19 ICS19

PrefaceSPRUE13A – September 2006Read This FirstAbout This ManualThis document describes the Serial RapidIO®(SRIO) peripheral on the TMS320TCI648x™ dev

www.ti.comSRIO RegistersTable 73. LSU Interrupt Condition Status Register (LSU_ICSR) Field Descriptions (continued)Bit Field Value Description1 ICS1 0

www.ti.com5.23 LSU Interrupt Condition Clear Register (LSU_ICCR)SRIO RegistersSetting a bit in this register clears the corresponding bit in LSU_ICSR,

www.ti.com5.24 Error, Reset, and Special Event Interrupt Condition Status RegisterSRIO Registers(ERR_RST_EVNT_ICSR)Each of the nonreserved bits in thi

www.ti.com5.25 Error, Reset, and Special Event Interrupt Condition Clear RegisterSRIO Registers(ERR_RST_EVNT_ICCR)Each bit in this register is used to

www.ti.com5.26 DOORBELL n Interrupt Condition Routing Registers (DOORBELL n_ICRR andSRIO RegistersDOORBELL n_ICRR2)When doorbell packets are received

www.ti.com5.27 RX CPPI Interrupt Condition Routing Registers (RX_CPPI_ICRR and RX_CPPI_ICRR2)SRIO RegistersFigure 88 and Table 79 summarize the ICRRs

www.ti.com5.28 TX CPPI Interrupt Condition Routing Registers (TX_CPPI_ICRR and TX_CPPI_ICRR2)SRIO RegistersFigure 89 and Table 80 summarize the ICRRs

www.ti.com5.29 LSU Interrupt Condition Routing Registers (LSU_ICRR0–LSU_ICRR3)SRIO RegistersFigure 90 shows the ICRRs for the LSU interrupt requests,

www.ti.comSRIO RegistersTable 81. LSU Interrupt Condition Routing Register Field DescriptionsField Value DescriptionICR x Interrupt condition routing.

www.ti.com5.30 Error, Reset, and Special Event Interrupt Condition Routing RegistersSRIO Registers(ERR_RST_EVNT_ICRR, ERR_RST_EVNT_ICRR2, and ERR_RST_

www.ti.comRelated Documentation From Texas InstrumentsTrademarksTMS320TCI648x, C6000, TMS320C62x, TMS320C67x, TMS320C6000, Code Composer Studio aretra

www.ti.com5.31 Interrupt Status Decode Register (INTDST n_DECODE)SRIO RegistersThere are eight of these registers, one for each interrupt destination

www.ti.comSRIO RegistersTable 84. Interrupt Status Decode Register (INTDST n_DECODE) Field Descriptions (continued)Bit Field Value Description27 ISD27

www.ti.comSRIO RegistersTable 84. Interrupt Status Decode Register (INTDST n_DECODE) Field Descriptions (continued)Bit Field Value Description15 ISD15

www.ti.comSRIO RegistersTable 84. Interrupt Status Decode Register (INTDST n_DECODE) Field Descriptions (continued)Bit Field Value Description7 ISD7 0

www.ti.com5.32 INTDST n Interrupt Rate Control Register (INTDST n_RATE_CNTL)SRIO RegistersThere are eight interrupt rate control registers, one for ea

www.ti.com5.33 LSU n Control Register 0 (LSU n_REG0)SRIO RegistersThere are four of these registers, one for each LSU (see Table 87 ). The general des

www.ti.com5.34 LSU n Control Register 1 (LSU n_REG1)SRIO RegistersThere are four of these registers, one for each LSU (see ). This register's con

www.ti.com5.35 LSU n Control Register 2 (LSU n_REG2)SRIO RegistersThere are four of these registers, one for each LSU (see Table 91 ). LSU n_REG2 is s

www.ti.com5.36 LSU n Control Register 3 (LSU n_REG3)SRIO RegistersThere are four of these registers, one for each LSU (see Table 93 ). LSU n_REG3 is s

www.ti.com5.37 LSU n Control Register 4 (LSU n_REG4)SRIO RegistersThere are four of these registers, one for each LSU (see Table 95 ). LSU n_REG4 is s

1 Overview1.1 General RapidIO System1.1.1 RapidIO Architectural HierarchyUser's GuideSPRUE13A – September 2006Serial RapidIO (SRIO)The RapidIO pe

www.ti.com5.38 LSU n Control Register 5 (LSU n_REG5)SRIO RegistersThere are four of these registers, one for each LSU (see Table 97 ). LSU n_REG5 is s

www.ti.com5.39 LSU n Control Register 6 (LSU n_REG6)SRIO RegistersThere are four of these registers, one for each LSU (see Table 99 ). LSU n_REG6 is s

www.ti.com5.40 LSU n Congestion Control Flow Mask Register (LSU n_FLOW_MASKS)SRIO RegistersThere are four of these registers, one for each LSU (see Ta

www.ti.comSRIO RegistersTable 103. LSU n FLOW_MASK Fields (continued)Bit Field Value Description8 FL8 0 LSU n does not support Flow 8 from table entry

www.ti.com5.41 Queue n Transmit DMA Head Descriptor Pointer Register (QUEUE n_TXDMA_HDP)SRIO RegistersThere are sixteen of these registers (see Table

www.ti.com5.42 Queue n Transmit DMA Completion Pointer Register (QUEUE n_TXDMA_CP)SRIO RegistersThere are sixteen of these registers (see Table 106 ).

www.ti.com5.43 Queue n Receive DMA Head Descriptor Pointer Register (QUEUE n_RXDMA_HDP)SRIO RegistersThere are sixteen of these registers (see Table 1

www.ti.com5.44 Queue n Receive DMA Completion Pointer Register (QUEUE n_RXDMA_CP)SRIO RegistersThere are sixteen of these registers (see Table 110 ).

www.ti.com5.45 Transmit Queue Teardown Register (TX_QUEUE_TEAR_DOWN)SRIO RegistersEach bit in this register corresponds to one of the 16 TX buffer des

www.ti.com5.46 Transmit CPPI Supported Flow Mask Registers (TX_CPPI_FLOW_MASKS[0–7])SRIO RegistersEach of the eight TX CPPI flow mask registers holds

www.ti.comGloballysharedmemory speclogicalFutureMessagepassingsystemI/OLogicalspecificationInformationnecessaryfortheendpointtoprocessthetran

www.ti.comSRIO RegistersFigure 108. Transmit CPPI Supported Flow Mask RegistersTransmit CPPI Supported Flow Mask Register 0 (TX_CPPI_FLOW_MASKS0)31 16

www.ti.comSRIO RegistersTable 114. TX Queue n FLOW_MASK Field Descriptions (continued)Bit Field Value Description12 FL12 0 Queue n does not support Fl

www.ti.com5.47 Receive Queue Teardown Register (RX_QUEUE_TEAR_DOWN)SRIO RegistersEach of this register's bits corresponds to one of the 16 RX buf

www.ti.com5.48 Receive CPPI Control Register (RX_CPPI_CNTL)SRIO RegistersEach bit in this register indicates whether the associated RX buffer descript

www.ti.com5.49 Transmit CPPI Weighted Round Robin Control Registers (TX_QUEUE_CNTL[0–3])SRIO RegistersThe transmission order among TX buffer descripto

www.ti.comSRIO RegistersTable 117. Transmit CPPI Weighted Round Robin Control Register Field DescriptionsField Pair Register[Bits] Field Value Descrip

www.ti.comSRIO RegistersTable 117. Transmit CPPI Weighted Round Robin Control Register Field Descriptions (continued)Field Pair Register[Bits] Field V

www.ti.com5.50 Mailbox to Queue Mapping Registers (RXU_MAP_L n and RXU_MAP_H n)SRIO RegistersMessages addressed to any of the 64 mailbox locations can

www.ti.comSRIO RegistersTable 118. Mailbox to Queue Mapping Registers and the Associated RXMappers (continued)Register Address Offset Associated RX Ma

www.ti.comSRIO RegistersFigure 113. Mailbox to Queue Mapping Register PairMailbox to Queue Mapping Register L n (RXU_MAP_L n )31 30 29 24 23 22 21 16L

www.ti.com1.1.2 RapidIO Interconnect ArchitectureHostSubsystemI/OControlSubsystemDSP FarmTDM,GMII,UtopiaCommunicationsSubsystem PCISubsystemInfi

www.ti.comSRIO RegistersTable 120. Mailbox-to-Queue Mapping Register H n (RXU_MAP_H n) Field Descriptions (continued)Bit Field Value Description7–6 Re

www.ti.com5.51 Flow Control Table Entry Register n (FLOW_CNTL n)SRIO RegistersThere are sixteen of these registers (see Table 121 ). FLOW_CNTL n is sh

www.ti.com5.52 Device Identity CAR (DEV_ID)SRIO RegistersThe device identity CAR (DEV_ID) is shown in Figure 115 and described in Table 123 . Writes h

www.ti.com5.53 Device Information CAR (DEV_INFO)SRIO RegistersThe device information CAR (DEV_INFO) is shown in Figure 116 and described in Table 124

www.ti.com5.54 Assembly Identity CAR (ASBLY_ID)SRIO RegistersThe assembly identity CAR (ASBLY_ID) is shown in Figure 117 and described in Table 125 .

www.ti.com5.55 Assembly Information CAR (ASBLY_INFO)SRIO RegistersThe assembly information CAR (ASBLY_INFO) is shown in Figure 118 and described in Ta

www.ti.com5.56 Processing Element Features CAR (PE_FEAT)SRIO RegistersThe processing element features CAR (PE_FEAT) is shown in Figure 119 and describ

www.ti.comSRIO RegistersTable 127. Processing Element Features CAR (PE_FEAT) Field Descriptions (continued)Bit Field Value Description2–0 EXTENDED_ADD

www.ti.com5.57 Source Operations CAR (SRC_OP)SRIO RegistersThe source operations CAR (SRC_OP) is shown in Figure 120 and described in Table 128 .Figur

www.ti.com5.58 Destination Operations CAR (DEST_OP)SRIO RegistersThe destination operations CAR (DEST_OP) is shown in Figure 121 and described in Tabl

www.ti.comSerialRapidIO1xDeviceto1xDeviceInterfaceDiagramSerialRapidIO4xDeviceto4xDeviceInterfaceDiagram1xDeviceTD[0]TD[0]RD[0]RD[0]

www.ti.com5.59 Processing Element Logical Layer Control CSR (PE_LL_CTL)SRIO RegistersThe processing element logical layer control CSR (PE_LL_CTL) is s

www.ti.com5.60 Local Configuration Space Base Address 0 CSR (LCL_CFG_HBAR)SRIO RegistersThe local configuration space base address 0 CSR (LCL_CFG_HBAR

www.ti.com5.61 Local Configuration Space Base Address 1 CSR (LCL_CFG_BAR)SRIO RegistersThe local configuration space base address 1 CSR (LCL_CFG_BAR)

www.ti.com5.62 Base Device ID CSR (BASE_ID)SRIO RegistersThe base device ID CSR (BASE_ID) is shown in Figure 125 and described in Table 133 .Figure 12

www.ti.com5.63 Host Base Device ID Lock CSR (HOST_BASE_ID_LOCK)SRIO RegistersSee Section 2.4.2 of the RapidIO Common Transport Specification for a des

www.ti.com5.64 Component Tag CSR (COMP_TAG)SRIO RegistersThe component Tag CSR (COMP_TAG) is shown in Figure 127 and described in Table 135 .Figure 12

www.ti.com5.65 1x/4x LP Serial Port Maintenance Block Header Register (SP_MB_HEAD)SRIO RegistersThe 1x/4x LP_Serial port maintenance block header regi

www.ti.com5.66 Port Link Time-Out Control CSR (SP_LT_CTL)SRIO RegistersThe port link time-out control CSR (SP_LT_CTL) is shown in Figure 129 and descr

www.ti.com5.67 Port Response Time-Out Control CSR (SP_RT_CTL)SRIO RegistersThe port response time-out control CSR (SP_RT_CTL) is shown in Figure 130 a

www.ti.com5.68 Port General Control CSR (SP_GEN_CTL)SRIO RegistersThe port general control CSR (SP_GEN_CTL) is shown in Figure 131 and described in Ta

2 SPRUE13A – September 2006Submit Documentation Feedback

www.ti.com1.3 Standards1.4 External Devices Requirements1.5 TI Devices Supported By This DocumentOverviewFeatures Not Supported:• Compliance with the

www.ti.com5.69 Port Link Maintenance Request CSR n (SP n_LM_REQ)SRIO RegistersEach of the four ports is supported by a register of this type (see Tabl

www.ti.com5.70 Port Link Maintenance Response CSR n (SP n_LM_RESP)SRIO RegistersEach of the four ports is supported by a register of this type (see Ta

www.ti.com5.71 Port Local AckID Status CSR n (SP n_ACKID_STAT)SRIO RegistersEach of the four ports is supported by a register of this type (see Table

www.ti.com5.72 Port Error and Status CSR n (SP n_ERR_STAT)SRIO RegistersEach of the four ports is supported by a register of this type (see Table 146

www.ti.comSRIO RegistersTable 147. Port Error and Status CSR n (SP n_ERR_STAT) Field Descriptions (continued)Bit Field Value Description23–21 Reserved

www.ti.comSRIO RegistersTable 147. Port Error and Status CSR n (SP n_ERR_STAT) Field Descriptions (continued)Bit Field Value Description1 PORT_OK Port

www.ti.com5.73 Port Control CSR n (SP n_CTL)SRIO RegistersEach of the four ports is supported by a register of this type (see Table 148 ). The port co

www.ti.comSRIO RegistersTable 149. Port Control CSR n (SP n_CTL) Field Descriptions (continued)Bit Field Value Description26–24 PORT_WIDTH_OVERRIDE Po

www.ti.comSRIO RegistersTable 149. Port Control CSR n (SP n_CTL) Field Descriptions (continued)Bit Field Value Description0 PORT_TYPE 1 Port type. Thi

www.ti.com5.74 Error Reporting Block Header Register (ERR_RPT_BH)SRIO RegistersThe Error Reporting Block Header Register (ERR_RPT_BH) is shown in Figu

www.ti.com2 SRIO Functional Description2.1 Overview2.1.1 Peripheral Data FlowSRIO Functional DescriptionThis peripheral is designed to be an externall

www.ti.com5.75 Logical/Transport Layer Error Detect CSR (ERR_DET)SRIO RegistersThis register allows for the detection of logical/transport layer error

www.ti.comSRIO RegistersTable 151. Logical/Transport Layer Error Detect CSR (ERR_DET) Field Descriptions (continued)Bit Field Value Description25 MSG_

www.ti.com5.76 Logical/Transport Layer Error Enable CSR (ERR_EN)SRIO RegistersThe logical/transport layer error enable CSR (ERR_EN) is shown in Figure

www.ti.comSRIO RegistersTable 152. Logical/Transport Layer Error Enable CSR (ERR_EN) Field Descriptions (continued)Bit Field Value Description24 PKT_R

www.ti.com5.77 Logical/Transport Layer High Address Capture CSR (H_ADDR_CAPT)SRIO RegistersThe logical/transport layer high address capture CSR (H_ADD

www.ti.com5.78 Logical/Transport Layer Address Capture CSR (ADDR_CAPT)SRIO RegistersThe logical/transport layer address capture CSR (ADDR_CAPT) is sho

www.ti.com5.79 Logical/Transport Layer Device ID Capture CSR (ID_CAPT)SRIO RegistersThe logical/transport layer device ID capture CSR (ID_CAPT) is sho

www.ti.com5.80 Logical/Transport Layer Control Capture CSR (CTRL_CAPT)SRIO RegistersThe logical/transport layer control capture CSR (CTRL_CAPT) is sho

www.ti.com5.81 Port-Write Target Device ID CSR (PW_TGT_ID)SRIO RegistersThe port-write target device ID CSR (PW_TGT_ID) is shown in Figure 144 and des

www.ti.com5.82 Port Error Detect CSR n (SP n_ERR_DET)SRIO RegistersEach of the four ports is supported by a register of this type (see Table 158 ). Th

www.ti.com1.25to3.125GbpsdifferentialdataRXClockrecoveryS2P10bClk8b/10bdecode8bClockrecoveryRX8b8b/10bdecode10bClkS2PClockrecoveryRX8b8b/10bdecode

www.ti.comSRIO RegistersTable 159. Port Error Detect CSR n (SP n_ERR_DET) Field Descriptions (continued)Bit Field Value Description20 RCVD_PKT_NOT_ACC

www.ti.com5.83 Port Error Rate Enable CSR n (SP n_RATE_EN)SRIO RegistersEach of the four ports is supported by a register of this type (see Table 160

www.ti.comSRIO RegistersTable 161. Port Error Rate Enable CSR n (SP n_RATE_EN) Field Descriptions (continued)Bit Field Value Description19 PKT_UNEXPEC

www.ti.com5.84 Port n Attributes Error Capture CSR 0 (SP n_ERR_ATTR_CAPT_DBG0)SRIO RegistersEach of the four ports is supported by a register of this

www.ti.com5.85 Port n Error Capture CSR 1 (SP n_ERR_CAPT_DBG1)SRIO RegistersEach of the four ports is supported by a register of this type (see Table

www.ti.com5.86 Port n Error Capture CSR 2 (SP n_ERR_CAPT_DBG2)SRIO RegistersEach of the four ports is supported by a register of this type (see Table

www.ti.com5.87 Port n Error Capture CSR 3 (SP n_ERR_CAPT_DBG3)SRIO RegistersEach of the four ports is supported by a register of this type (see Table

www.ti.com5.88 Port n Error Capture CSR 4 (SP n_ERR_CAPT_DBG4)SRIO RegistersEach of the four ports is supported by a register of this type (see Table

www.ti.com5.89 Port Error Rate CSR n (SP n_ERR_RATE)SRIO RegistersEach of the four ports is supported by a register of this type (see Table 172 ). SP

www.ti.com5.90 Port Error Rate Threshold CSR n (SP n_ERR_THRESH)SRIO RegistersEach of the four ports is supported by a register of this type (see ). T

www.ti.comInitiatorRequestPacketIssuedOperationCompletedforMasterAcknowledgeSymbolAcknowledgeSymbolResponsePacketForwardedRequestPacketForwardedAck

www.ti.com5.91 Port IP Discovery Timer for 4x Mode Register (SP_IP_DISCOVERY_TIMER)SRIO RegistersThe port IP discovery timer for 4x mode register (SP_

www.ti.com5.92 Port IP Mode CSR (SP_IP_MODE)SRIO RegistersThe port IP mode CSR (SP_IP_MODE) is shown in Figure 155 and described in Table 177 . For ad

www.ti.comSRIO RegistersTable 177. Port IP Mode CSR (SP_IP_MODE) Field Descriptions (continued)Bit Field Value Description3 RST_EN Reset Interrupt Ena

www.ti.com5.93 Port IP Prescaler Register (IP_PRESCAL)SRIO RegistersThe port IP prescaler register (IP_PRESCAL) is shown in Figure 156 and described i

www.ti.com5.94 Port-Write-In Capture CSRs (SP_IP_PW_IN_CAPT[0–3])SRIO RegistersFour registers are used to capture the incoming 128-bit payload of a Po

www.ti.com5.95 Port Reset Option CSR n (SP n_RST_OPT)SRIO RegistersEach of the four ports is supported by a register of this type (see Table 180 ). SP

www.ti.com5.96 Port Control Independent Register n (SP n_CTL_INDEP)SRIO RegistersEach of the four ports is supported by a register of this type (see T

www.ti.comSRIO RegistersTable 183. Port Control Independent Register n (SP n_CTL_INDEP) Field Descriptions (continued)Bit Field Value Description23 DE

www.ti.com5.97 Port Silence Timer n Register (SP n_SILENCE_TIMER)SRIO RegistersEach of the four ports is supported by a register of this type (see Tab

www.ti.com5.98 Port Multicast-Event Control Symbol Request Register n (SP n_MULT_EVNT_CS)SRIO RegistersEach of the four ports is supported by a regist

www.ti.comdouble-word04double-wordn-1acklD rsvpriott ftypedestIDsourcelDaddressrsrvxamsbsdouble-word1...double-wordn-2CRCPHYLOGTRALOGTRAPHY5322882

www.ti.com5.99 Port Control Symbol Transmit n Register (SP n_CS_TX)SRIO RegistersEach of the four ports is supported by a register of this type (see T

IndexSPRUE13A – September 2006Index1x/4x LP serial port maintenance block header registernext expected ackID field 202196output port next transmitted

SRIO RegistersBYTE_COUNT field of LSUn_REG3 158Bbad CRC in control symbol at port nCrate counting enable field 221CAPTURE0 field of SPn_ERR_CAPT_DBG1

SRIO Registersat port n requesting interrupt with INTERRUPT_REQ field 159CRC errorsrate counting enable field 222bad CRC in control symbol at port nst

SRIO RegistersDEV_INFO 183 doorbell interrupt condition status registers 132DEVICE_VENDORIDENTITY field of DEV_ID 182 DOORBELLn_ICCR 133DEVICEID_MSB f

SRIO RegistersENPLL2 field of PER_SET_CNTL 113 register 142ENPLL3 field of PER_SET_CNTL 113 ERROR responseENPLL4 field of PER_SET_CNTL 113during direc

SRIO Registersinterrupt condition clearing 86Ginterrupt condition clear registersGBL_EN 116for CPPI interrupt conditions 135 , 137GBL_EN_STAT 117for d

SRIO Registerslimiting which devices can access a mailbox 45 LSU_ICSR 138line rate versus PLL output clock frequency 29 LSU congestion control flow ma

SRIO RegistersMAX_RETRY_ERR field of SPn_CTL_INDEP 236 MMRs enable bit 119MAX_RETRY_THR field of SPn_CTL_INDEP 236 MMRs enable status bits 118 , 120ma

SRIO RegistersOUTBOUND_ACKID field of SPn_ACKID_STAT 202 packet response timeout at LSU or TXUoutbound credit 75reporting enable field 213status field

www.ti.com2.1.2.4 SRIO Packet Type2.2 SRIO PinsSRIO Functional DescriptionThe type of received packet determines how the packet routing is handled. Re

SRIO Registersin SRIO component block diagram 26 port multicast-event control symbol request registers239PID register 111port n error capturepins/diff

SRIO RegistersPW_DIS field of SP_IP_MODE 231 read support for destination device 189PW_EN field of SP_IP_MODE 231 read support for source device 188PW

SRIO RegistersSERDES macrosfor doorbell interrupt conditions 144for error, reset, and special event (port) interrupt configuration example 35condition

SRIO RegistersSPn_ERR_CAPT_DBG1 224 SWING field of SERDES_CFGTXn_CNTL 128SPn_ERR_CAPT_DBG2 225 switch capability field 186SPn_ERR_CAPT_DBG3 226 SWITCH

SRIO Registerstransmitter enabling for SERDES macro status field 219unexpected ackID in packet at port nintroduction 33transmitter enable bit 129rate

SRIO RegistersXoff 65 Xon 65SPRUE13A – September 2006 Index 255Submit Documentation Feedback

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www.ti.com2.3 Functional Operation2.3.1 Component Block DiagramSRIO Functional DescriptionTable 4. Pin DescriptionPin SignalPin Name Count Direction D

www.ti.comPort08x276 TX8x276RX8x276RX8x276 TXPort18x276 TX8x276RXPort28x276RX8x276 TXPort3PhysicallayerbuffersSERDES0 SERDES

www.ti.com2.3.2 SERDES Macro and its Configurations2.3.2.1 Enabling the PLLSRIO Functional DescriptionSRIO offers many benefits to customers by allowi

www.ti.comSRIO Functional DescriptionTable 5. SERDES Macro Configuration Register 0 (SERDES_CFG0_CNTL) Field DescriptionsBit Field Value Description31

ContentsPreface ... 141 Ove

www.ti.com2.3.2.2 Enabling the ReceiverSRIO Functional DescriptionTable 6. Line Rate versus PLL Output Clock FrequencyRate Line Rate PLL Output Freque

www.ti.comSRIO Functional DescriptionThe clock recovery algorithms listed in the CDR bits operate to adjust the clocks used to sample thereceived mess

www.ti.comSRIO Functional DescriptionTable 9. SERDES Receive Channel Configuration Register n (SERDES_CFGRX n_CNTL) FieldDescriptions (continued)Bit F

www.ti.com2.3.2.3 Enabling the TransmitterSRIO Functional DescriptionTable 9. SERDES Receive Channel Configuration Register n (SERDES_CFGRX n_CNTL) Fi

www.ti.comSRIO Functional DescriptionTable 11. SERDES Transmit Channel Configuration Register n (SERDES_CFGTX n_CNTL) FieldDescriptions (continued)Bit

www.ti.com2.3.2.4 SERDES Configuration Example2.3.3 Direct I/O OperationSRIO Functional DescriptionTable 13. SWING Bits of SERDES_CFGTX n_CNTLSWING Bi

www.ti.comLSU _REG0n RapidIO AddressMSB Control31RapidIO AddressLSB/Config_offset Control31 0LSU _REG1nDSP Address Control31 0LSU _REG2nRSV Control3

www.ti.comSRIO Functional DescriptionTable 14. LSU Control/Command Register Fields (continued)LSU Register Field RapidIO Packet Header FieldDestID Rap

www.ti.comLSU _REG1nT0T1 T2T3T4 T5TnValidLSU _REG2nValidLSU _REG3nValidLSU _REG4nValidLSU _REG5nValidRdy/BSYCompletionValid ValidAfter TransactionCom

www.ti.comSource AddressDMA ReadDestination AddressCountByteCountDSP AddressRSVInterruptReq001723 8DestID25 24IDSize27 26xambs29 28PriorityOutPortI

5.23 LSU Interrupt Condition Clear Register (LSU_ICCR) ... 1415.24 Error, Reset, and Special Event In

www.ti.comLSU2LSU4LSU3LSU1MMRcommandUDILoad/StoremoduleRapidIOtransportandphysicallayersPortxtransmissionFIFOqueuesTXFIFORXFIFOPeripheralboun

www.ti.comSRIO Functional DescriptionData leaves the shared TX buffer sequentially in order of receipt, not based on the packet priority.However, if f

www.ti.com2.3.3.3 Direct I/O RX OperationSRIO Functional DescriptionSegmentation:The LSU handles two types of segmentation of outbound requests. The f

www.ti.com2.3.3.4 Reset and Power Down State2.3.4 Message PassingSRIO Functional DescriptionSo the general flow is as follows:• Previously, the contro

www.ti.com2.3.4.1 RX OperationMailbox1...64fromRapidIOpacketHeader-ReceivedonanyinputportMailboxmapperQ15Q2 Q1Q0QueueassignabletoanycoreP

www.ti.comacklD rsv prio tt ftypeftype=1011destIDsourcelD msglen ssize msgseg/xmbox double-word0 double-word1 ...double-wordn-2 double-wordn-1 C

www.ti.comSRIO Functional DescriptionFigure 18. Mailbox to Queue Mapping Register PairMailbox to Queue Mapping Register L n (RXU_MAP_L n )31 30 29 24

www.ti.com310121523727 1119329ownershipteardowneopeoqsop3reservedccmessage_length1321525917 1301422626 10182281220424816 0BitFieldsnext_descriptor_po

www.ti.comSRIO Functional DescriptionTable 18. RX Buffer Descriptor Field Descriptions (continued)Field Descriptionownership Ownership: Indicates owne

www.ti.comSwitchSwitchEndpointEndpointC0C0B0B0B2B2A1A1B1B1A0A0OpenOpenOpenOpenOpenOpenOpenFullOpenOpenFullFullRetryRetryRetryRetryRetryRetryAcceptRetr

5.69 Port Link Maintenance Request CSR n (SP n_LM_REQ) ... 2005.70 Port Link Maintenance Response CSR n (

www.ti.comSRIO Functional DescriptionIn addition, multiple messages can be interleaved at the receive port due to ordering within a connectedswitch’s

www.ti.comCPPIblockCPUDMAConfigbusaccessL2memoryBufferdescriptordual-portSRAM(Nx20B)Data bufferPeripheralboundary323232128CPPI controlregisters2.

www.ti.com310121523727 1119329ownershipteardowneopeoqsop3reservedretry_countccmessage_length1321525917 1301422626 10182281220424816 0BitFieldsnext_de

www.ti.comSRIO Functional DescriptionTable 21. TX Buffer Descriptor Field Definitions (continued)Field Descriptionretry_count Message Retry Count: Set

www.ti.comSRIO Functional DescriptionTable 21. TX Buffer Descriptor Field Definitions (continued)Field Descriptionssize RIO standard message payload s

www.ti.comSRIO Functional DescriptionTX_Queue_Map has been programmed to send two messages from Queue 0 before moving to Queue 1,it will re-attempt to

www.ti.comSRIO Functional DescriptionFigure 23. Weighted Round Robin Programming Registers (Address Offset 7E0h–7ECh)TX_QUEUE_CNTL0 - Address Offset 7

www.ti.comSRIO Functional DescriptionTable 22. Weighted Round Robin Programming Registers (Address Offset 7E0h–7ECh) (continued)Field Pair Register[Bi

www.ti.comSRIO Functional DescriptionTable 22. Weighted Round Robin Programming Registers (Address Offset 7E0h–7ECh) (continued)Field Pair Register[Bi

www.ti.com2.3.4.3 Reset and Power Down StateSRIO Functional DescriptionA transaction timeout is used by all outgoing message and direct I/O packets. I

List of Figures1 RapidIO Architectural Hierarchy ... 172 RapidI

www.ti.com2.3.4.4 Message Passing Software RequirementsSRIO Functional DescriptionSoftware performs the following functions for messaging:RX Operation

www.ti.comSRIO Functional DescriptionInitialization ExampleSRIO_REGS->Queue0_RXDMA_HDP = 0 ;SRIO_REGS->Queue1_RXDMA_HDP = 0 ;SRIO_REGS->Queue

www.ti.comDescriptorDescriptorBufferBufferPortRXDMAstateRXqueueheaddescriptorpointerSRIO Functional DescriptionFigure 24. RX Buffer DescriptorsTX

www.ti.comDescriptorDescriptorBufferBufferPort TXDMAstateTXqueueheaddescriptorpointer2.3.5 Maintenance2.3.6 Doorbell OperationSRIO Functional Desc

www.ti.comacklD rsv prio tt 1010 destID sourcelD Reserved srcTIDReserved DoorbellReg# rsvDoorbellbitCRCPHYLOGTRALOGTRAPHY5 3 2 2 4 8 8 8 89 2141616

www.ti.com2.3.7 Atomic Operations2.3.8 Congestion ControlSRIO Functional DescriptionSRIO_REGS->LSU1_REG0 = CSL_FMK( SRIO_LSU1_REG0_RAPIDIO_ADDRESS_

www.ti.com2.3.8.1 Detailed DescriptionReservedFLOW_CNTL031-18R-0x00000TT17-16R/W-01FLOW_CNTL_ID15-0R/W-0x0000ReservedFLOW_CNTL131-18R-0x00000TT17-16R/

www.ti.comReservedRIO_LSUn_FLOW_MASKS(AddressOffsets:0x041C,0x043C,0x045C,0x047C)31-16R,0x0000LSUnFlowMask15-0R/W,0xFFFFTXQueue1FlowMaskRIO

www.ti.com2.3.9 EndiannessSRIO Functional DescriptionTable 25. Fields Within Each Flow MaskBit Field Value Description15 FL15 0 TX source does not sup

www.ti.com2.3.9.1 Translation for MMR spaceA0A0A2A2A1A1A3A3L2offset0x0DSP definedMMRoffset0x1000Bytelane031Bytelane3DMA 32b02.3.9.2 Endian Conve

50 RX CPPI Interrupt Condition Status and Clear Registers ... 8951 TX CPPI Interrupt Conditi

www.ti.com2.3.10 Reset and Power DownSRIO Functional DescriptionThe RapidIO peripheral allows independent software controlled shutdown for the logical

www.ti.com2.3.10.1 Reset and Power Down Summary2.3.10.2 Enable and Enable Status RegistersSRIO Functional DescriptionAfter reset, the state of the per

www.ti.comSRIO Functional DescriptionTable 27. Global Enable and Global Enable Status Field DescriptionsRegister (Bit) Field Value DescriptionGBL_EN(3

www.ti.comSRIO Functional DescriptionFigure 35. BLK0_EN_STAT (Address 003Ch)31 1 0Reserved EN_STATR-0 R-1LEGEND: R = Read, W = Write, - n = Value afte

www.ti.com2.3.10.3 Software Shutdown Details2.3.11 EmulationSRIO Functional DescriptionPower consumption is minimized for all logical blocks that are

www.ti.com2.3.12 TX Buffers, Credit, and Packet Reordering2.3.12.1 Multiple Ports With 1x OperationSRIO Functional DescriptionTable 29. Peripheral Con

www.ti.com2.3.12.2 Single Port With 1x or 4x Operation2.3.12.3 Unavailable Outbound CreditSRIO Functional DescriptionThe physical layer buffers act li

www.ti.com2.3.13 Initialization Example2.3.13.1 Enabling the SRIO Peripheral2.3.13.2 PLL, Ports, Device ID and Data Rate InitializationsSRIO Functiona

www.ti.com2.3.13.3 Peripheral InitializationsSRIO Functional DescriptionSRIO_REGS->SERDES_CFG0_CNTL = 0x00000013;SRIO_REGS->SERDES_CFG1_CNTL = 0

www.ti.com2.3.14 Bootload Capability2.3.14.1 Configuration and OperationSRIO Functional DescriptionSRIO_REGS->SP_RT_CTL = 0xFFFFFF00; // longSRIO_R

102 LSU n FLOW_MASK Fields ... 162103 Queue n Transmit DMA

www.ti.comBootProgramHostControllerOptionalI2CEEPROMDSPROM1xRapidIO2.3.14.2 Bootload Data Movement2.3.14.3 Device Wakeup2.3.15 RX Multicast Support,

www.ti.com2.3.15.2 Daisy Chain Operation and Packet Forwarding2.3.15.3 Enabling Multicast and Packet ForwardingSRIO Functional DescriptionTable 31. Mu

www.ti.comSRIO Functional DescriptionFigure 43. Packet Forwarding Register n for 8-Bit Device IDs (PF_8B_CNTL n) Offsets 0x0094,0x009C, 0x00A4, 0x00AC

www.ti.com3 Logical/Transport Error Handling and LoggingLogical/Transport Error Handling and LoggingError management registers allow detection and log

www.ti.comLogical/Transport Error Handling and LoggingTable 34. Logical/Transport Layer Error Detect CSR (ERR_DET) Field Descriptions (continued)Bit F

www.ti.com4 Interrupt Conditions4.1 CPU Interrupts4.2 General DescriptionacklD rsv prio tt 1010 destID sourcelD Reserved srcTIDReserved DoorbellReg#

www.ti.com4.3 Interrupt Condition Status and Clear RegistersInterrupt ConditionsThe DOORBELL packet’s 16-bit INFO field indicates which DOORBELL regis

www.ti.com4.3.1 Doorbell Interrupt Condition Status and Clear RegistersInterrupt ConditionsTable 35. Interrupt Condition Status and Clear BitsField Ac

www.ti.com4.3.2 CPPI Interrupt Condition Status and Clear RegistersInterrupt ConditionsFigure 48. Doorbell 2 Interrupt Condition Status and Clear Regi

www.ti.com4.3.3 LSU Interrupt Condition Status and Clear RegistersInterrupt ConditionsFor transmission, the clearing of any ICSR bit is dependent on t

155 Port IP Mode CSR (SP_IP_MODE) - Address Offset 12004h ... 231156 Port IP Prescaler Register (IP

www.ti.comInterrupt ConditionsFigure 52. LSU Interrupt Condition Status and Clear RegistersLSU Interrupt Condition Status Register (LSU_ICSR) (Address

www.ti.com4.3.4 Error, Reset, and Special Event Interrupt Condition Status and Clear RegistersInterrupt ConditionsTable 36. Interrupt Conditions Shown

www.ti.comInterrupt ConditionsThe interrupt status bits found in the ERR_RST_EVNT (0x0270) can be cleared by writing to the ICCRregister (0x0278) in t

www.ti.com4.4 Interrupt Condition Routing Registers4.4.1 Doorbell Interrupt Condition Routing RegistersInterrupt ConditionsTable 38. Interrupt Clearin

www.ti.com4.4.1.1 CPPI Interrupt Condition Routing RegistersInterrupt ConditionsWhen doorbell packets are received by the SRIO peripheral, these ICRRs

www.ti.com4.4.1.2 LSU Interrupt Condition Routing RegistersInterrupt ConditionsFigure 56. TX CPPI Interrupt Condition Routing RegistersTX CPPI Interru

www.ti.com4.4.1.3 Error, Reset, and Special Event Interrupt Condition Routing RegistersInterrupt ConditionsFigure 57. LSU Interrupt Condition Routing

www.ti.com4.5 Interrupt Status Decode RegistersInterrupt ConditionsFigure 58. Error, Reset, and Special Event Interrupt Condition Routing RegistersErr

www.ti.comInterrupt Conditionseach bit in the ISDR. Bits within the LSU interrupt condition status register (ICSR) are logically grouped fora given co

www.ti.com4.6 Interrupt Generation4.7 Interrupt PacingInterrupt ConditionsFigure 61. Example Diagram of Interrupt Status Decode Register MappingThe fo