Texas-instruments TMS320DM643X DMP Manuel d'utilisateur Page 1

TMS320DM643x DMPUniversal Asynchronous Receiver/Transmitter(UART)User's GuideLiterature Number: SPRU997CDecember 2009

Divisor +UART input clock frequencyDesired baud rate 16ProcessorgeneratorClockDLH:DLLUART input clockDSP input clockUARTReceivertiming andcontrolTra

BCLKEach bit lasts 16 BCLK cycles.When receiving, the UART samples the bit in the 8th cycle.D0TX,RXD1 D2PARITYD7D6D5STOP2STOP1D1 D4D2 D3STARTD0TX,RXUA

Peripheral Architecturewww.ti.com2.2 Signal DescriptionsThe UARTs utilize a minimal number of signal connections to interface with external devices. T

www.ti.comPeripheral Architecture2.4.3 Data FormatThe UART transmits in the following format:1 START bit + data bits (5, 6, 7, 8) + 1 PARITY bit (opti

Peripheral Architecturewww.ti.com2.6 Operation2.6.1 TransmissionThe UART transmitter section includes a transmitter hold register (THR) and a transmit

www.ti.comPeripheral Architecture2.6.3 FIFO ModesThe following two modes can be used for servicing the receiver and transmitter FIFOs:• FIFO interrupt

rtsReceiverFIFOD[7:0]UARTSerial toParallelFlowControlTransmitterFIFOParallel toSerialFlowControlParallel toSerialFlowControlSerial toParallelFlowContr

RXRTSStart Start StartStopStopBits NBits N+1Start StopTXCTSStart StopBits0−7 Start StopBits 0−7 Start StopBits 0−7www.ti.comPeripheral Architecture2.6

Peripheral Architecturewww.ti.com2.7 Reset Considerations2.7.1 Software Reset ConsiderationsTwo bits in the power and emulation management register (P

UART interruptrequest to CPUIER(ETBEI)IER(ERBI)Transmitter holdingregister emptyReceiver data readyTHREINTRDRINTOverrun errorIER(ELSI)RTOINTConditions

2SPRU997C–December 2009Submit Documentation FeedbackCopyright © 2009, Texas Instruments Incorporated

Peripheral Architecturewww.ti.com2.10 DMA Event SupportIn the FIFO mode, the UART generates the following two DMA events:• Receive event (URXEVT): The

www.ti.comRegisters2.13 Exception Processing2.13.1 Divisor Latch Not ProgrammedSince the processor reset signal has no effect on the divisor latch, th

Registerswww.ti.com3.1 Receiver Buffer Register (RBR)The receiver buffer register (RBR) is shown in Figure 9 and described in Table 7.The UART receive

www.ti.comRegisters3.2 Transmitter Holding Register (THR)The transmitter holding register (THR) is shown in Figure 10 and described in Table 8.The UAR

Registerswww.ti.com3.3 Interrupt Enable Register (IER)The interrupt enable register (IER) is used to individually enable or disable each type of inter

www.ti.comRegisters3.4 Interrupt Identification Register (IIR)The interrupt identification register (IIR) is a read-only register at the same address

Registerswww.ti.comTable 11. Interrupt Identification and Interrupt Clearing InformationIIR BitsPriorityLevel 3 2 1 0 Interrupt Type Interrupt Source

www.ti.comRegistersFigure 13. FIFO Control Register (FCR)31 16ReservedR-015 8ReservedR-07 6 5 4 3 2 1 0RXFIFTL Reserved DMAMODE1(1)TXCLR RXCLR FIFOENW

Registerswww.ti.com3.6 Line Control Register (LCR)The line control register (LCR) is shown in Figure 14 and described in Table 13.The system programme

www.ti.comRegistersTable 13. Line Control Register (LCR) Field Descriptions (continued)Bit Field Value Description2 STB Number of STOP bits generated.

Preface ... 61 Int

Registerswww.ti.com3.7 Modem Control Register (MCR)The modem control register (MCR) is shown in Figure 15 and described in Table 16. The modem control

www.ti.comRegisters3.8 Line Status Register (LSR)The line status register (LSR) is shown in Figure 16 and described in Table 17. LSR provides informat

Registerswww.ti.comTable 17. Line Status Register (LSR) Field Descriptions (continued)Bit Field Value Description4 BI Break indicator. The BI bit is s

www.ti.comRegistersTable 17. Line Status Register (LSR) Field Descriptions (continued)Bit Field Value Description0 DR Data-ready (DR) indicator for th

Registerswww.ti.comFigure 17. Divisor LSB Latch (DLL)31 16ReservedR-015 8 7 0Reserved DLLR-0 R/W-0LEGEND: R/W = Read/Write; R = Read only; -n = value

www.ti.comRegisters3.10 Peripheral Identification Registers (PID1 and PID2)The peripheral identification registers (PID) contain identification data (

Registerswww.ti.com3.11 Power and Emulation Management Register (PWREMU_MGMT)The power and emulation management register (PWREMU_MGMT) is shown in Fig

www.ti.comAppendix A Revision HistoryTable 23 lists the changes made since the previous version of this document.Table 23. Document Revision HistoryRe

IMPORTANT NOTICETexas Instruments Incorporated and its subsidiaries (TI) reserve the right to make corrections, modifications, enhancements, improveme

www.ti.comList of Figures1 UART Block Diagram... 9

www.ti.comList of Tables1 UART Supported Features/Characteristics by Instance ... 82 Baud

PrefaceSPRU997C–December 2009Read This FirstAbout This ManualThis document describes the universal asynchronous receiver/transmitter (UART) peripheral

User's GuideSPRU997C–December 2009Universal Asynchronous Receiver/Transmitter (UART)1 IntroductionThis document describes the universal asynchron

Introductionwww.ti.comTable 1 summarizes the capabilities supported on the UART. Note that the number of UARTs and theirsupported features vary on eac

8ReceiverBufferRegisterDivisorLatch (LS)DivisorLatch (MS)BaudGeneratorReceiverFIFOLine StatusRegisterTransmitterHoldingRegisterModem ControlRegisterLi